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Barton Sano: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese
    Piranha: a scalable architecture based on single-chip multiprocessing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:282-293 [Conf]
  2. Bruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Ralph Clarke Haygood, William R. Bush, Alvin M. Despain, Joan M. Pendleton, Tep P. Dobry
    Fast Prolog with an Extended General Purpose Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:282-291 [Conf]
  3. Apoorv Srivastava, Yong-Seon Koh, Barton Sano, Alvin M. Despain
    190-MHz CMOS 4-Kbyte Pipelined Caches. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1053-1056 [Conf]
  4. Barton Sano, Alvin M. Despain
    The 16-fold way: a microparallel taxonomy. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:60-69 [Conf]
  5. Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
    Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:14-24 [Conf]
  6. Bruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Alvin M. Despain
    Design and Analysis of Hardware for High-Performance Prolog. [Citation Graph (0, 0)][DBLP]
    J. Log. Program., 1996, v:29, n:1-3, pp:107-139 [Journal]
  7. Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
    Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:9, pp:934-946 [Journal]

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