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Leonard M. Napolitano Jr.: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Leonard M. Napolitano Jr.
    A Computer Architecture for Dynamic Finite Element Analysis. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:316-323 [Conf]
  2. Leonard M. Napolitano Jr.
    The Design of a High Performance Packet-Switched Network. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1990, v:10, n:2, pp:103-114 [Journal]
  3. G. Robert Redinbo, Leonard M. Napolitano Jr., David D. Andaleon
    Multibit Correcting Data Interface for Fault-Tolerant Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:4, pp:433-446 [Journal]

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