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Kari Halonen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mikko Aho, Väinö Hakkarainen, Lauri Sumanen, Mikko Waltari, Kari Halonen
    An IF-sampling timing skew-insensitive parallel S/H circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:1052-1055 [Conf]
  2. Väinö Hakkarainen, Lauri Sumanen, Mikko Aho, Mikko Waltari, Kari Halonen
    A self-calibration technique for time-interleaved pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:825-828 [Conf]
  3. Kari Halonen, Kimmo Koli, Jukka Wallinheimo, Harri Kimppa
    An Integrated Fully-Differential Switched-Current Ladder Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:313-316 [Conf]
  4. Kari Halonen, Veikko Porra, P. Alinikula, K. Koli, H. Riihihuhta, J. Hännikäinen
    Integrated BiCMOS IF-Modules for Mobile Telecommunication Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:661-664 [Conf]
  5. Saku Hamalainen, Lauri Koskinen, Kari Halonen
    A hardware-based predictive motion estimation algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6114-6117 [Conf]
  6. Mikko Hotti, Jussi Ryynänen, Kalle Kivekäs, Kari Halonen
    An IIP2 calibration technique for direct conversion receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:257-260 [Conf]
  7. Jarkko Jussila, Kari Halonen
    Minimization of power dissipation of analog channel-select filter and Nyquist-rate A/D converter in UTRA/FDD. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:940-943 [Conf]
  8. Asko Kananen, Mika Laiho, Kari Halonen, Ari Paasio
    N /spl times/ 16 cellular test chips for low-pass filtering large images. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:461-464 [Conf]
  9. Jarkko Jussila, Kari Halonen
    Programmable-gain amplifiers based on AC couplings for continuous reception. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:801-804 [Conf]
  10. J. Kaukovuori, Mikko Hotti, Jussi Ryynänen, Jarkko Jussila, Kari Halonen
    A linearized 2-GHz SiGe low noise amplifier for direct conversion receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:200-203 [Conf]
  11. Jaakko Ketola, Johan Sommarek, Jouko Vankka, Kari Halonen
    Transmitter utilising bandpass delta-sigma modulator and switching mode power amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:633-636 [Conf]
  12. Jaakko Ketola, Jouko Vankka, Kari Halonen
    Synchronization of fractional interval counter in non-integer ratio sample rate converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:89-92 [Conf]
  13. Kimmo Koli, Kari Halonen
    A BiCMOs Current-Feedback Operational Amplifier with a 60 dB Constant Bandwidth Range. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:525-528 [Conf]
  14. Lauri Koskinen, Ari Paasio, Kari Halonen
    3-neighborhood motion estimation in CNN silicon architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:708-711 [Conf]
  15. Marko Kosunen, Jouko Vankka, F. Teikari, Kari Halonen
    DNL and INL yield models for a current-steering D/A converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:969-972 [Conf]
  16. Mika Laiho, Ari Paasio, Kari Halonen
    Improved cell core for a mixed-mode polynomial CNN. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:93-96 [Conf]
  17. Arto Malinen, Kari Stadius, Kari Halonen
    Characteristics and modeling of a broadband transmission-line transformer. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:413-416 [Conf]
  18. Ari Paasio, Jacek Flak, Mika Laiho, Kari Halonen
    High density VLSI implementation of a bipolar CNN with reduced programmability. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:21-24 [Conf]
  19. Ari Paasio, Kari Halonen, Veikko Porra
    CMOS Implementation of Associative Memory Using Cellular Neural Network Having Adjustable Template Coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:487-490 [Conf]
  20. Ari Paasio, Mika Laiho, Asko Kananen, Kari Halonen, Jonne Poikonen
    A 32×32 cellular test chip targeting new functionalities. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:506-509 [Conf]
  21. Jussi Pirkkalaniemi, Marko Kosunen, Mikko Waltari, Kari Halonen
    A digital calibration for a 16-bit, 400-MHz current-steering DAC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:297-300 [Conf]
  22. H. Riihihuhta, Kari Halonen, Kari Koli
    A High Dynamic Range 100Mhz AGC-Amplifier with a Linear and Temperature Compensated Gain Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:521-524 [Conf]
  23. Jaana Riikonen, Mikko Aho, Väinö Hakkarainen, Kari Halonen, Lauri Sumanen
    A 10-bit 400-MS/s 170 mW 4-times interleaved A/D converter in 0.35µm BiCMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4622-4625 [Conf]
  24. Jussi Ryynänen, Mikko Hotti, Kari Halonen
    IIP2 calibration methods for current output mixer in direct-conversion receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5059-5062 [Conf]
  25. Mikko Saukoski, Lasse Aaltonen, Kari Halonen
    Fully integrated charge pump for high voltage excitation of a bulk micromachined gyroscope. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5381-5384 [Conf]
  26. Mikko Saukoski, Lasse Aaltonen, Teemu Salo, Kari Halonen
    Fully integrated charge sensitive amplifier for readout of micromechanical capacitive sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5377-5380 [Conf]
  27. Teemu Salo, Saska Lindfors, Kari Halonen
    BP decimation filter for IF-sampling merged with BP /spl Sigma//spl Delta/-modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1017-1020 [Conf]
  28. Kari Stadius, Kari Halonen
    Development of 4-GHz flip-chip VCO module. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2687-2690 [Conf]
  29. Kari Stadius, Arto Malinen, Petteri Paatsila, Kari Halonen
    A broadband upconverter unit for double-conversion receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:177-180 [Conf]
  30. Esa Tiiliharju, Kari Halonen
    A biased low-voltage BiCMOS mixer for direct up-conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:33-36 [Conf]
  31. Jouko Vankka, Jaakko Lindeberg, Kari Halonen
    Direct digital synthesizer with tunable phase and amplitude error feedback structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:785-788 [Conf]
  32. Jouko Vankka, Jonne Lindeberg, Kari Halonen
    Direct digital synthesizer with tunable delta sigma modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:917-920 [Conf]
  33. Lauri Sumanen, Kari Halonen
    A single-amplifier 6-bit CMOS pipeline A/D converter for WCDMA receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:584-587 [Conf]
  34. Teemu Salo, Saska Lindfors, Kari Halonen
    A low-voltage single-Opamp 4th-order band-pass Sigma-Delta-modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:352-355 [Conf]
  35. T. Hollman, Saska Lindfors, Teemu Salo, M. Lansirinne, Kari Halonen
    A 2.7 V CMOS dual-mode baseband filter for GSM and WCDMA. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:316-319 [Conf]
  36. Kari Stadius, P. Jarvio, Petteri Paatsila, Kari Halonen
    Image-reject receivers with image-selection functionality. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:124-127 [Conf]
  37. Risto Kaunisto, P. Korpi, J. Kiraly, Kari Halonen
    A linear-control wide-band CMOS attenuator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:458-461 [Conf]
  38. Kalle Kivekäs, A. Parssinen, Jarkko Jussila, Jussi Ryynänen, Kari Halonen
    Design of low-voltage active mixer for direct conversion receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:382-385 [Conf]
  39. Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
    Discrete time analog polynomial type CNN with digital state. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:497-500 [Conf]
  40. Saska Lindfors, M. Lansirinne, T. Lindeman, Kari Halonen
    On the design of 2nd order multi-bit Sigma-Delta-modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:13-16 [Conf]
  41. Mikko Waltari, Kari Halonen
    Timing skew insensitive switching for double sampled circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:61-64 [Conf]
  42. R. Ahola, Kari Stadius, Kari Halonen
    Design of a fully integrated 2 GHz CMOS frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:160-163 [Conf]
  43. Jouko Vankka, Marko Kosunen, Kari Halonen
    Multicarrier QAM modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:415-418 [Conf]
  44. Ari Paasio, Asko Kananen, Kari Halonen
    Very fast and compact fixed template CNN realizations for B/W processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 1999, pp:595-598 [Conf]
  45. Jarkko Jussila, Kari Halonen
    WCDMA channel selection filter with high IIP2. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:533-536 [Conf]
  46. Jussi Pirkkalaniemi, Marko Waltari, Mikko Kosunen, Lauri Sumanen, Kari Halonen
    A 14-bit, 40-MS/s DAC with current mode deglitcher. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:121-124 [Conf]
  47. Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
    Cell and network level design of a mixed-mode CNN. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:621-624 [Conf]
  48. Jussi Ryynänen, Kalle Kivekäs, Jarkko Jussila, A. Parssinen, Kari Halonen
    RF gain control in direct conversion receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:117-120 [Conf]
  49. Lauri Koskinen, Ari Paasio, Mika Laiho, Kari Halonen
    Effect of CNN shape segmentation on MPEG-4 shape bit-rate. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:552-555 [Conf]
  50. Jouko Vankka, Jonne Lindeberg, Kari Halonen
    FIR filters for compensating D/A converter frequency response distortion. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:105-108 [Conf]
  51. Esa Tiiliharju, Kari Halonen
    A quadrature-modulator for 0.6-2.6 GHz with frequency doubler. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:429-432 [Conf]
  52. Lauri Sumanen, Mikko Waltari, Väinö Hakkarainen, Kari Halonen
    CMOS dynamic comparators for pipeline A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:157-160 [Conf]
  53. Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
    Realization of Couplings in a Polynomial Type Mixed-Mode Cellular Neural Network. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 2003, v:13, n:6, pp:443-452 [Journal]
  54. Lauri Koskinen, Ari Paasio, Kari Halonen
    Motion estimation computational complexity reduction with CNN shape segmentation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:6, pp:771-777 [Journal]
  55. Marko Kosunen, Jouko Vankka, Mikko Waltari, Kari Halonen
    A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:181-190 [Journal]
  56. Jere A. M. Jarvinen, Mikko Saukoski, Kari Halonen
    A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1713-1716 [Conf]
  57. Matti Paavola, Mikko Saukoski, Mika Laiho, Kari Halonen
    A Micropower Voltage, Current, and Temperature Reference for a Low-Power Capacitive Sensor Interface. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3067-3070 [Conf]
  58. Ville Saari, Jussi Ryynänen, J. Mustola, Kari Halonen, Jarkko Jussila
    A 10-MHz channel-select filter for a multicarrier WCDMA base-station. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  59. T. Tikka, Jussi Ryynänen, Mikko Hotti, Kari Halonen
    Design of a high linearity mixer for direct-conversion base-station receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  60. Matti Paavola, Mika Laiho, Mikko Saukoski, Kari Halonen
    A 3µW, 2 MHz CMOS frequency reference for capacitive sensor applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  61. Architecture for Analog Variable Block-Size Motion Estimation. [Citation Graph (, )][DBLP]


  62. Template design for binary-programmable cellular nonlinear networks. [Citation Graph (, )][DBLP]


  63. Parallel processor algorithm for variable block-size computation at low bitrates [video coding applications]. [Citation Graph (, )][DBLP]


  64. Centroiding and classification of objects using a processor array with a scalable region of interest. [Citation Graph (, )][DBLP]


  65. Compass tilt compensation algorithm using CORDIC. [Citation Graph (, )][DBLP]


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