The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Øivind Næss: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yngvar Berg, Snorre Aunet, Øivind Næss, Johannes Goplen Lomsdalen, Mats Høvin
    Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:345-348 [Conf]
  2. Øivind Næss, Espen A. Olsen, Yngvar Berg, Tor Sverre Lande
    A low voltage second order biquad using pseudo floating-gate transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:125-128 [Conf]
  3. Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin
    Extreme low-voltage floating-gate CMOS transconductance amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:37-40 [Conf]
  4. Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
    Floating-gate CMOS differential analog inverter for ultra low-voltage applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:9-12 [Conf]
  5. Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
    Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:838-841 [Conf]
  6. Yngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin
    A novel floating-gate multiple-valued CMOS full-adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:877-880 [Conf]
  7. Øivind Næss, Yngvar Berg
    Tunable floating-gate low-voltage transconductor. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:663-666 [Conf]
  8. Yngvar Berg, Øivind Næss, Snorre Aunet, R. Jensen, Mats Høvin
    Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:385-388 [Conf]
  9. Yngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari
    Basic Multiple-Valued Functions Using Recharge CMOS Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:346-351 [Conf]
  10. Øivind Næss, Yngvar Berg
    Switched pseudo floating-gate reconfigurable linear threshold elements. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

Search in 0.002secs, Finished in 0.003secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002