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Publications of Author

1. Peter Celinski, Derek Abbott, Sorin Dan Cotofana
   Area efficient, high speed parallel counter circuits using charge recycling threshold logic. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:233-236 [Conf]
   
2. Peter Celinski, Said F. Al-Sarawi, Derek Abbott, J. F. Lopez
   Low depth carry lookahead addition using charge recycling threshold logic. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2002, pp:469-472 [Conf]
   
3. Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis
   Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2004, pp:127-134 [Conf]
   
4. Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi, Michael J. Liebelt
   Hybrid Parallel Counters - Domino and Threshold Logic. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2004, pp:275-276 [Conf]
   
5. Peter Celinski, Sorin Cotofana, Derek Abbott
   A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. [Citation Graph (0, 0)][DBLP]
   IWANN (2), 2003, pp:73-80 [Conf]
   
6. Peter Celinski, Derek Abbott, Sorin Cotofana
   Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2004, pp:899-906 [Conf]