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Li-Hsun Chen:
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- Li-Hsun Chen, Oscal T.-C. Chen
A hardware-efficient FIR architecture with input-data and tap folding. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2005, pp:544-547 [Conf]
- Li-Hsun Chen, Oscal T.-C. Chen, Ruey-Ling Ma
A high-efficiency reconfigurable digital signal processor for multimedia computing. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2003, pp:768-771 [Conf]
- Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Yung-Cheng Ma
A multiplication-accumulation computation unit with optimized compressors and minimized switching activities. [Citation Graph (0, 0)][DBLP] ISCAS (6), 2005, pp:6118-6121 [Conf]
- Li-Hsun Chen, Oscal T.-C. Chen
A low-complexity and high-speed Booth-algorithm FIR architecture. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2001, pp:338-341 [Conf]
- Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Chi-Lung Wang
An adaptive DSP processor for high-efficiency computing MPEG-4 video encoder. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:157-160 [Conf]
- Oscal T.-C. Chen, Li-Hsun Chen, N.-W. Lin, Chih-Chang Chen
Application-Specific Data Path for Highly Efficient Computation of Multistandard Video Codecs. [Citation Graph (0, 0)][DBLP] IEEE Trans. Circuits Syst. Video Techn., 2007, v:17, n:1, pp:26-42 [Journal]
A Low-Power Folded Programmable FIR Architecture. [Citation Graph (, )][DBLP]
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