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Publications of Author

1. P. C. Chen, James B. Kuo
   Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:441-444 [Conf]
   
2. James B. Kuo, H. P. Chen, H. J. Huang
   A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1993, pp:2027-2030 [Conf]
   
3. James B. Kuo, B. Y. Chen, Mark W. Mao
   A Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSI. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:331-334 [Conf]
   
4. James B. Kuo, K. W. Su, J. H. Lou
   A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:323-326 [Conf]
   
5. Mark W. Mao, B. Y. Chen, James B. Kuo
   A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1993, pp:1967-1970 [Conf]
   
6. James B. Kuo
   Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited. [Citation Graph (0, 0)][DBLP]
   IWSOC, 2005, pp:143-148 [Conf]
   
7. Mark W. Mao, James B. Kuo
   A coded block adaptive neural network system with a radical-partitioned structure for large-volume Chinese characters recognition. [Citation Graph (0, 0)][DBLP]
   Neural Networks, 1992, v:5, n:5, pp:835-841 [Journal]
   
8. Y. G. Chen, James B. Kuo
   A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:256-258 [Journal]
   
9. H.-C. Chow, W.-S. Feng, James B. Kuo
   An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1522-1528 [Journal]
   
10. James B. Kuo, G. P. Rosseel, Robert W. Dutton
    Two-dimensional analysis of a merged BiPMOS device. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:929-932 [Journal]
    
11. James B. Kuo, Tsen-Shau Yang, Robert W. Dutton, Bruce A. Wooley
    Two-dimensional transient analysis of a collector-up ECL inverter. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1038-1045 [Journal]
    
12. Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki
    Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:453-462 [Conf]
    
13. 
    Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. [Citation Graph (, )][DBLP]