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Jun-Hong Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu
    Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5254-5257 [Conf]
  2. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo
    VLSI architecture exploration for sliding-window Log-MAP decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:513-516 [Conf]
  3. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen
    VLSI architectural design tradeoffs for sliding-window log-MAP decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:439-447 [Journal]
  4. Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin
    A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3780-3783 [Conf]
  5. Ming-Der Shieh, Yung-Kuei Lu, Shen-Ming Chung, Jun-Hong Chen
    Design and implementation of efficient Reed-Solomon decoders for multi-mode applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  6. Jing-Shiun Lin, Chung-Kung Lee, Ming-Der Shieh, Jun-Hong Chen
    High-speed CRC design for 10 Gbps applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  7. High-speed modular multiplication design for public-key cryptosystems. [Citation Graph (, )][DBLP]

  8. A new look-up table-based multiplier/squarer design for cryptosystems over GF(2m). [Citation Graph (, )][DBLP]

  9. Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation. [Citation Graph (, )][DBLP]

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