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Shu-Yu Jiang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang
    A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1174-1177 [Conf]
  2. Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen
    BIST for clock jitter measurements. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:577-580 [Conf]
  3. Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang
    Static divided word matching line for low-power Content Addressable Memory design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:629-632 [Conf]
  4. Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang
    Self-sampled vernier delay line for built-in clock jitter measurement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

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