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Wei-Bin Yang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang
    A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1174-1177 [Conf]
  2. Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo
    A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:777-780 [Conf]
  3. Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung
    A low-power high driving ability voltage control oscillator used in PLL. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:614-617 [Conf]
  4. Chung-Yu Chang, Wei-Ben Yang, Ching-Ji Huang, Cheng-Hsing Chien
    New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3740-3743 [Conf]
  5. Shu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang
    The new improved pseudo fractional-N clock generator with 50% duty cycle. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  6. A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. [Citation Graph (, )][DBLP]

  7. 0.5V 160-MHz 260uW all digital phase-locked loop. [Citation Graph (, )][DBLP]

  8. Analysis and Design of High Performance, Low Power Multiple Ports Register Files. [Citation Graph (, )][DBLP]

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