|
Search the dblp DataBase
Brian S. Cherkauer:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Brian S. Cherkauer, Eby G. Friedman
The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs. [Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:2110-2113 [Conf]
- Brian S. Cherkauer, Eby G. Friedman
Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design. [Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:111-114 [Conf]
- Stefan Rusu, Harry Muljono, Brian S. Cherkauer
Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2004, v:24, n:2, pp:10-18 [Journal]
- Brian S. Cherkauer, Eby G. Friedman
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:100-114 [Journal]
- Brian S. Cherkauer, Eby G. Friedman
A unified design methodology for CMOS tapered buffers. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:99-111 [Journal]
Search in 0.003secs, Finished in 0.003secs
|