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Publications of Author

1. Carlos H. Díaz, Charvaka Duvvury, Sung-Mo Kang
   Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1993, pp:1389-1392 [Conf]
   
2. Charvaka Duvvury
   ESD: Design For IC Chip Quality and Reliability. [Citation Graph (0, 0)][DBLP]
   ISQED, 2000, pp:251-0 [Conf]
   
3. Charvaka Duvvury
   Issues in Deep Submicron State-of-the-Art ESD Design. [Citation Graph (0, 0)][DBLP]
   ISQED, 2001, pp:10- [Conf]
   
4. Charvaka Duvvury
   Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
   ISQED, 2002, pp:8- [Conf]
   
5. Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury
   Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:482-493 [Journal]
   
6. Craig Salling, Jerry Hu, Jeff Wu, Charvaka Duvvury, Roger Cline, Rith Pok
   Development of substrate-pumped nMOS protection for a 0.13 mum technology. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2002, v:42, n:6, pp:887-899 [Journal]
   
7. Jorge Salcedo-Suñer, Charvaka Duvvury, Roger Cline, Alfonso Cadena-Hernandez
   Latchup in voltage tolerant circuits: a new phenomenon. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2004, v:44, n:4, pp:549-562 [Journal]
   
8. Charvaka Duvvury, Robert Steinhoff, Gianluca Boselli, Vijay Reddy, Hans Kunz, Steve Marum, Roger Cline
   Gate oxide failures due to anomalous stress from HBM ESD testers. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2006, v:46, n:5-6, pp:656-665 [Journal]