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Publications of Author

1. Piotr Dudek
   A flexible global readout architecture for an analogue SIMD vision chip. [Citation Graph (0, 0)][DBLP]
   ISCAS (3), 2003, pp:782-785 [Conf]
   
2. Piotr Dudek
   A 39/spl times/48 general-purpose focal-plane processor array integrated circuit. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2004, pp:448-452 [Conf]
   
3. Piotr Dudek
   Implementation of SIMD vision chip with 128×128 array of analogue processing elements. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 2005, pp:5806-5809 [Conf]
   
4. P. Dudek, P. J. Hicks
   An analogue SIMD focal-plane processor array. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2001, pp:490-493 [Conf]
   
5. David Lopez Vilarino, Piotr Dudek
   Evolution of Pixel Level Snakes towards an efficient hardware implementation. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:2678-2681 [Conf]
   
6. A. Lopich, P. Dudek
   Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
7. 
   Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks. [Citation Graph (, )][DBLP]
   
   
8. 
   Using Reinforcement Learning to Guide the Development of Self-organised Feature Maps for Visual Orienting. [Citation Graph (, )][DBLP]
   
   
9. 
   Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit. [Citation Graph (, )][DBLP]
   
   
10. 
    Implementation of multi-layer leaky integrator networks on a cellular processor array. [Citation Graph (, )][DBLP]
    
    
11. 
    Integrated circuit implementation of a cortical neuron. [Citation Graph (, )][DBLP]
    
    
12. 
    ASPA: Focal Plane digital processor array with asynchronous processing capabilities. [Citation Graph (, )][DBLP]
    
    
13. 
    Focal-plane moving object segmentation for realtime video surveillance. [Citation Graph (, )][DBLP]