A. Lopich, P. Dudek Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks. [Citation Graph (, )][DBLP]
Using Reinforcement Learning to Guide the Development of Self-organised Feature Maps for Visual Orienting. [Citation Graph (, )][DBLP]
Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit. [Citation Graph (, )][DBLP]
Implementation of multi-layer leaky integrator networks on a cellular processor array. [Citation Graph (, )][DBLP]
Integrated circuit implementation of a cortical neuron. [Citation Graph (, )][DBLP]
ASPA: Focal Plane digital processor array with asynchronous processing capabilities. [Citation Graph (, )][DBLP]
Focal-plane moving object segmentation for realtime video surveillance. [Citation Graph (, )][DBLP]
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