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Publications of Author

1. Andrea Gerosa, Andrea Neviani
   A very low-power 8-bit Sigma-Delta converter in a 0.8µm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:49-52 [Conf]
   
2. Andrea Maniero, Andrea Gerosa, Andrea Neviani
   Performance optimization in micro-power, low-voltage log-domain filters in pure CMOS technology. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2003, pp:565-568 [Conf]
   
3. Matteo Perenzoni, Andrea Gerosa, Andrea Neviani
   Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block turbo code. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:813-816 [Conf]
   
4. Andrea Xotta, Andrea Gerosa, Andrea Neviani
   A multi-mode Sigma-Delta analog-to-digital converter for GSM, UMTS and WLAN. [Citation Graph (0, 0)][DBLP]
   ISCAS (3), 2005, pp:2551-2554 [Conf]
   
5. Andrea Gerosa, Arianna Novo, A. Mengalli, Andrea Neviani
   A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2001, pp:296-299 [Conf]
   
6. Andrea Gerosa, Andrea Neviani
   A low-power decimation filter for a sigma-delta converter based on a power-optimized sinc filter. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2004, pp:245-248 [Conf]
   
7. Andrea Xotta, Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, M. Bruccoleri, G. Betti
   An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2002, pp:69-72 [Conf]
   
8. Andrea Gerosa, Arianna Novo, Andrea Neviani
   Low-power sensing and digitization of cardiac signals based on sigma-delta conversion (poster session). [Citation Graph (0, 0)][DBLP]
   ISLPED, 2000, pp:216-218 [Conf]
   
9. Alessandra Nardi, Andrea Neviani, Carlo Guardiani
   Realistic Worst-Case Modeling by Performance Level Principal Component Analysis. [Citation Graph (0, 0)][DBLP]
   ISQED, 2000, pp:455-460 [Conf]
   
10. Stefano Zanella, Andrea Neviani, Enrico Zanoni, Paolo Miliozzi, Edoardo Charbon, Carlo Guardiani, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Modeling of Substrate Noise Injected by Digital Libraries. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:488-0 [Conf]
    
11. Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa
    Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Communications, 2006, v:54, n:6, pp:1143- [Journal]
    
12. Andrea Bevilacqua, Christoph Sandner, Andrea Gerosa, Andrea Neviani
    Quadrature VCOs Based on Coupled PLLs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2140-2143 [Conf]
    
13. Andrea Gerosa, M. Soldan, Alessandro Bevilacqua, Andrea Neviani
    A 0.18-µm CMOS Squarer Circuit for a Non-Coherent UWB Receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:421-424 [Conf]
    
14. Andrea Gerosa, Andrea Bevilacqua, Andrea Neviani, Andrea Xotta
    An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
15. Alexandre Graell i Amat, Daniele Vogrig, Sergio Benedetto, Guido Montorsi, Andrea Neviani, Andrea Gerosa
    Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
    
16. 
    An energy-detector for non-coherent impulse-radio UWB receivers. [Citation Graph (, )][DBLP]
    
    
17. 
    Analog decoding of trellis coded modulation for multi-level flash memories. [Citation Graph (, )][DBLP]
    
    
18. 
    Design of broadband inductorless LNAs in ultra-scaled CMOS technologies. [Citation Graph (, )][DBLP]