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Anantha P. Chandrakasan:
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Publications of Author
- Brian P. Ginsburg, Anantha P. Chandrakasan
An energy-efficient charge recycling approach for a SAR converter with capacitive DAC. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2005, pp:184-187 [Conf]
- Joyce Kwong, Anantha P. Chandrakasan
Variation-driven device sizing for minimum energy sub-threshold circuits. [Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:8-13 [Conf]
- Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. [Citation Graph (0, 0)][DBLP] SLIP, 2005, pp:65-72 [Conf]
- Benton H. Calhoun, Denis C. Daly, Naveen Verma, Daniel F. Finchelstein, David D. Wentzloff, Alice Wang, Seong-Hwan Cho, Anantha P. Chandrakasan
Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2005, v:54, n:6, pp:727-740 [Journal]
- Anantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan M. Rabaey, Robert W. Brodersen
Optimizing power using transformations. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:12-31 [Journal]
- Miodrag Potkonjak, Mani B. Srivastava, Anantha P. Chandrakasan
Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:151-165 [Journal]
- Mani B. Srivastava, Anantha P. Chandrakasan, Robert W. Brodersen
Predictive system shutdown and other architectural techniques for energy efficient programmable computation. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:42-55 [Journal]
- Vadim Gutnik, Anantha P. Chandrakasan
Embedded power supply for low-power DSP. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:425-435 [Journal]
- Seong-Hwan Cho, Thucydides Xanthopoulos, Anantha P. Chandrakasan
A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:249-257 [Journal]
- Abram P. Dancy, Rajeevan Amirtharajah, Anantha P. Chandrakasan
High-efficiency multiple-output DC-DC conversion for low-voltage systems. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:252-263 [Journal]
- Manish Bhardwaj, Rex Min, Anantha P. Chandrakasan
Quantifying and enhancing power awareness of VLSI systems. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:757-772 [Journal]
- Paul-Peter Sotiriadis, Anantha P. Chandrakasan
A bus energy model for deep submicron technology. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:341-350 [Journal]
- Amit Sinha, Nathan Ickes, Anantha P. Chandrakasan
Instruction level and operating system profiling for energy exposed software. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1044-1057 [Journal]
- Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif
Wiring requirement and three-dimensional integration technology for field programmable gate arrays. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:44-54 [Journal]
The design of a low power carbon nanotube chemical sensor system. [Citation Graph (, )][DBLP]
The mixed signal optimum energy point: voltage and parallelism. [Citation Graph (, )][DBLP]
Parallel CABAC for low power video coding. [Citation Graph (, )][DBLP]
A high throughput CABAC algorithm using syntax element partitioning. [Citation Graph (, )][DBLP]
Ultra-low-power UWB for sensor network applications. [Citation Graph (, )][DBLP]
A 0.4-V UWB baseband processor. [Citation Graph (, )][DBLP]
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