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Un-Ku Moon: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon
    Jitter in high-speed serial and parallel links. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:425-428 [Conf]
  2. Min Gyu Kim, Gil-Cho Ahn, Un-Ku Moon
    An improved algorithmic ADC clocking scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:589-592 [Conf]
  3. Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
    A low spur fractional-N frequency synthesizer architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2807-2810 [Conf]
  4. Volodymyr Kratyuk, Igor Vytyaz, Un-Ku Moon, Kartikeya Mayaram
    Analysis of supply and ground noise sensitivity in ring and LC oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5986-5989 [Conf]
  5. Jipeng Li, Un-Ku Moon
    An extended radix-based digital calibration technique for multi-stage ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:829-832 [Conf]
  6. Un-Ku Moon, Bang-Sup Song
    Low-distortion Continuous-time R-MOSFET-C Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1168-1171 [Conf]
  7. Anurog Pulincherry, Mike Hufford, Eric Naviasky, Un-Ku Moon
    Continuous-time, frequency translating, bandpass delta-sigma modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1013-1016 [Conf]
  8. Thirumalai Rengachari, Vivek Sharma, Gabor C. Temes, Un-Ku Moon
    A 10-bit algorithmic A/D converter for cytosensor application. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6186-6189 [Conf]
  9. Vivek Sharma, Un-Ku Moon, Gabor C. Temes
    A generic multilevel multiplying D/A converter for pipelined ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6182-6185 [Conf]
  10. José Silva, Un-Ku Moon, Gabor C. Temes
    Low-distortion delta-sigma topologies for MASH architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:1144-1147 [Conf]
  11. Shelly Xiao, José Silva, Un-Ku Moon, Gabor C. Temes
    A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:433-436 [Conf]
  12. M. Keskin, Un-Ku Moon, Gabor C. Temes
    Low-voltage low-sensitivity switched-capacitor bandpass Sigma-Delta modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:348-351 [Conf]
  13. Peter Kiss, Un-Ku Moon, Jesper Steensgaard, John T. Stonick, Gabor C. Temes
    Multibit Sigma-Delta ADC with mixed-mode DAC error correction. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:280-283 [Conf]
  14. R. Perigny, Un-Ku Moon, Gabor C. Temes
    Area efficient CMOS charge pump circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:492-495 [Conf]
  15. B. R. Greenley, Un-Ku Moon, R. Veith
    A 1.8 V CMOS DAC cell with ultra high gain op-amp in 0.0143 mm2. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:412-415 [Conf]
  16. Jesper Steensgaard, Un-Ku Moon, Gabor C. Temes
    Mismatch-shaping serial digital-to-analog converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:5-8 [Conf]
  17. Zhiliang Zheng, Un-Ku Moon, Jesper Steensgaard, Bo Wang, Gabor C. Temes
    Capacitor mismatch error cancellation technique for a successive approximation A/D converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:326-329 [Conf]
  18. E. Bidari, M. Keskin, Franco Maloberti, Un-Ku Moon, Jesper Steensgaard, Gabor C. Temes
    Low-voltage switched-capacitor circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:49-52 [Conf]
  19. Jipeng Li, Un-Ku Moon
    High-speed pipelined A/D converter using time-shifted CDS technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:909-912 [Conf]
  20. A. Rao, W. McIntyre, J. Parry, Un-Ku Moon, Gabor C. Temes
    Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:743-746 [Conf]
  21. Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram
    Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:424-429 [Conf]
  22. Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram
    Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1073-1076 [Conf]
  23. Sunwoo Kwon, Un-Ku Moon
    A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:733-736 [Conf]
  24. Nima Maghari, Sunwoo Kwon, Gabor C. Temes, Un-Ku Moon
    Mixed-Order Sturdy MASH Delta-Sigma Modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:257-260 [Conf]
  25. B. Robert Gregoire, Un-Ku Moon
    Process-Independent Resistor Temperature-Coefficients using Series/Parallel and Parallel/Series Composite Resistors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2826-2829 [Conf]
  26. N. Talebbeydokhti, Pavan Kumar Hanumolu, P. Kurahashi, Un-Ku Moon
    Constant transconductance bias circuit with an on-chip resistor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. Ting Wu, Un-Ku Moon, Kartikeya Mayaram
    Dependence of LC VCO oscillation frequency on bias current. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. J. Carnes, Un-Ku Moon
    The effect of switch resistance on pipelined ADC MDAC settling time. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  29. Periodic Steady-State Analysis Augmented with Design Equality Constraints. [Citation Graph (, )][DBLP]

  30. Sensitivity analysis for oscillators. [Citation Graph (, )][DBLP]

  31. An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. [Citation Graph (, )][DBLP]

  32. Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer. [Citation Graph (, )][DBLP]

  33. Multi-loop efficient sturdy MASH delta-sigma modulators. [Citation Graph (, )][DBLP]

  34. Parameter variation analysis for voltage controlled oscillators in phase-locked loops. [Citation Graph (, )][DBLP]

  35. Reducing the effects of component mismatch by using relative size information. [Citation Graph (, )][DBLP]

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