Shen-Fu Hsiao, Wei-Ren Shiue A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array. [Citation Graph (0, 0)][DBLP] IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:11, pp:1149-1159 [Journal]
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. [Citation Graph (, )][DBLP]
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. [Citation Graph (, )][DBLP]
An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches. [Citation Graph (, )][DBLP]
An Automatic Cache Generator Based on Content-Addressable Memory. [Citation Graph (, )][DBLP]
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. [Citation Graph (, )][DBLP]
Partition methodology for the final adder in a tree-structure parallel multiplier generator. [Citation Graph (, )][DBLP]
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