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Shen-Fu Hsiao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen
    An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2433-2436 [Conf]
  2. Shen-Fu Hsiao
    A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:455-458 [Conf]
  3. Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng
    Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:34-42 [Conf]
  4. Shen-Fu Hsiao, Jean-Marc Delosme
    Householder CORDIC Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:8, pp:990-1001 [Journal]
  5. Shen-Fu Hsiao, Wei-Ren Shiue
    A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:11, pp:1149-1159 [Journal]

  6. An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. [Citation Graph (, )][DBLP]


  7. Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. [Citation Graph (, )][DBLP]


  8. An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches. [Citation Graph (, )][DBLP]


  9. An Automatic Cache Generator Based on Content-Addressable Memory. [Citation Graph (, )][DBLP]


  10. Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. [Citation Graph (, )][DBLP]


  11. Partition methodology for the final adder in a tree-structure parallel multiplier generator. [Citation Graph (, )][DBLP]


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