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Publications of Author

1. Chin-Shan Hsieh, Hong-Yi Huang, Jeng-Dang Juan, Ruey-Nan Yeh
   A high-bandwidth wireless infrared receiver with feedforward offset extractor. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2003, pp:73-76 [Conf]
   
2. Chun-Jen Huang, Hong-Yi Huang
   A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2004, pp:673-676 [Conf]
   
3. Hong-Yi Huang, Chung-Yu Wu
   Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1993, pp:1905-1908 [Conf]
   
4. Hong-Yi Huang, Chung-Yu Wu
   New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:15-18 [Conf]
   
5. Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu
   Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:1572-1575 [Conf]
   
6. Hong-Yi Huang, Teng-Neng Wang
   High-speed CMOS logic circuits in capacitor coupling technique. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2001, pp:634-637 [Conf]
   
7. Hong-Yi Huang, Jing-Fu Lin
   CMOS bulk input technique. [Citation Graph (0, 0)][DBLP]
   ISCAS (3), 2002, pp:253-256 [Conf]
   
8. Hong-Yi Huang, Hsuan-Yi Su
   Low-power 2P2N SRAM with column hidden refresh. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2002, pp:591-594 [Conf]
   
9. Hong-Yi Huang, Shih-Lun Chen
   Input isolated sense amplifiers. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2002, pp:587-590 [Conf]
   
10. Hong-Yi Huang, Shih-Lun Chen
    Interconnect accelerating techniques for sub-100-nm gigascale systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1192-1200 [Journal]
    
11. Hong-Yi Huang, Sheng-Da Wu, Yi-Jui Tsai
    A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2160-2163 [Conf]
    
12. Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu
    High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
13. Hong-Yi Huang, Ching-Chieh Wu, Sen-Da Wu
    On-chip bidirectional transceiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
14. Hong-Yi Huang, Chia-Ming Liang, Wei-Ming Chiu
    1-99% input duty 50% output duty cycle corrector. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
15. 
    0.5V 160-MHz 260uW all digital phase-locked loop. [Citation Graph (, )][DBLP]
    
    
16. 
    Analysis and optimization of ring oscillator using sub-feedback scheme. [Citation Graph (, )][DBLP]
    
    
17. 
    A 64-MHz/spl sim/1920-MHz programmable spread-spectrum clock generator. [Citation Graph (, )][DBLP]
    
    
18. 
    Low-power 50% duty cycle corrector. [Citation Graph (, )][DBLP]
    
    
19. 
    Dual band LNA/mixer using conjugate matching for implantable biotelemetry. [Citation Graph (, )][DBLP]
    
    
20. 
    Multiple bulk input differential logic. [Citation Graph (, )][DBLP]
    
    
21. 
    Threshold triggers and accelerator for deep submicron interconnection. [Citation Graph (, )][DBLP]
    
    
22. 
    All digital time-to-digital converter using single delay-locked loop. [Citation Graph (, )][DBLP]
    
    
23. 
    A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator. [Citation Graph (, )][DBLP]