The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Seng-Pan U.: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins
    A frequency up-conversion and two-step channel selection embedded CMOS D/A interface. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:392-395 [Conf]
  2. Chon-In Lao, Ho-leng Leong, Kuoi-Fok Au, Kuok-Hang Mok, Seng-Pan U., Rui Paulo Martins
    A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:1061-1064 [Conf]
  3. Pui-In Mak, Kin-Kwan Ma, Weng-leng Mok, Chi-sam Sou, Kit-man Ho, Cheng-Man Ng, Seng-Pan U., Rui Paulo Martins
    An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:1068-1071 [Conf]
  4. Pui-In Mak, Seng-Pan U., Rui Paulo Martins
    A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:417-420 [Conf]
  5. Pui-In Mak, Man-Chung Wong, Seng-Pan U.
    A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:948-951 [Conf]
  6. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca
    Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:129-132 [Conf]
  7. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:369-372 [Conf]
  8. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1585-1588 [Conf]
  9. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1581-1584 [Conf]
  10. Seng-Pan U., Rui Paulo Martins, José E. Franca
    High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:204-207 [Conf]
  11. Seng-Pan U., Rui Paulo Martins, José E. Franca
    A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:320-323 [Conf]
  12. Seng-Pan U., Rui Paulo Martins, José E. Franca
    Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:57-60 [Conf]
  13. Seng-Pan U., Rui Paulo Martins, José E. Franca
    High performance multirate SC circuits with predictive correlated double sampling technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:77-80 [Conf]
  14. Seng-Pan U., Rui Paulo Martins, José E. Franca
    Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:441-444 [Conf]
  15. Weng-leng Mok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins
    A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1947-1950 [Conf]
  16. Chon-In Lao, Seng-Pan U., Rui Paulo Martins
    A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  17. Kin-Sang Chio, Seng-Pan U., Rui Paulo Martins
    A dual-mode low-distortion sigma-delta modulator with relaxing comparator accuracy. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  18. Pui-In Mak, Seng-Pan U., Rui Paulo Martins
    Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  19. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  20. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  21. A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators. [Citation Graph (, )][DBLP]


  22. A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA. [Citation Graph (, )][DBLP]


  23. A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. [Citation Graph (, )][DBLP]


  24. A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique. [Citation Graph (, )][DBLP]


Search in 0.102secs, Finished in 0.103secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002