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Ming-Dou Ker: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu
    A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:41-44 [Conf]
  2. Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai
    A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:321-324 [Conf]
  3. Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai
    Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1859-1862 [Conf]
  4. Ming-Dou Ker, Chien-Ming Lee
    Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:297-300 [Conf]
  5. Ming-Dou Ker, Chia-Sheng Tsai
    Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:97-100 [Conf]
  6. Ming-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang, Tao Cheng, Tain-Shun Wu
    Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:833-836 [Conf]
  7. Kun-Hsien Lin, Ming-Dou Ker
    ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1182-1185 [Conf]
  8. Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Win
    ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:754-757 [Conf]
  9. Ming-Dou Ker, Tung-Yan Chen
    Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:758-761 [Conf]
  10. Ming-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen
    ESD buses for whole-chip ESD protection. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:545-548 [Conf]
  11. Che-Hao Chuang, Ming-Dou Ker
    Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:577-580 [Conf]
  12. Shih-Lun Chen, Ming-Dou Ker
    A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:573-576 [Conf]
  13. Ming-Dou Ker, Kun-Hsien Lin
    ESD protection design for IC with power-down-mode operation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:717-720 [Conf]
  14. Ming-Dou Ker, Kuo-Chun Hsu
    On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:529-532 [Conf]
  15. Ming-Dou Ker, Che-Hao Chuang
    ESD protection circuits with novel MOS-bounded diode structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:533-536 [Conf]
  16. Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang
    Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:537-540 [Conf]
  17. Tung-Yang Chen, Ming-Dou Ker
    Design on ESD Protection Circuit with Very Low and Constant Input Capacitance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:247-248 [Conf]
  18. Hsin-Chyh Hsu, Ming-Dou Ker
    Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:503-506 [Conf]
  19. Ming-Dou Ker, Wen-Yi Chen
    Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:445-450 [Conf]
  20. Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo
    ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:331-336 [Conf]
  21. Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo
    Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:433-438 [Conf]
  22. Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng
    Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:363-368 [Conf]
  23. Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, M.-C. Wang
    Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:267-272 [Conf]
  24. Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang
    Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:241-0 [Conf]
  25. Tai-Xiang Lai, Ming-Dou Ker
    Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:597-602 [Conf]
  26. Ming-Dou Ker, Yu-Yu Sung
    Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:3, pp:417-429 [Journal]
  27. Ming-Dou Ker, Chyh-Yih Chang
    ESD protection design for CMOS RF integrated circuits using polysilicon diodes. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:6, pp:863-872 [Journal]
  28. Wen-Yu Lo, Ming-Dou Ker
    Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1583-1588 [Journal]
  29. I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming-Dou Ker
    Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:8, pp:1295-1301 [Journal]
  30. Chih-Yao Huang, Wei-Fang Chen, Song-Yu Chuan, Fu-Chien Chiu, Jeng-Chou Tseng, I-Cheng Lin, Chuan-Jane Chao, Len-Yi Leu, Ming-Dou Ker
    Design optimization of ESD protection and latchup prevention for a serial I/O IC. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:2, pp:213-221 [Journal]
  31. Shih-Hung Chen, Ming-Dou Ker
    Investigation on seal-ring rules for IC product reliability in 0.25-mum CMOS technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:9-11, pp:1311-1316 [Journal]
  32. Chih-Kang Deng, Ming-Dou Ker
    ESD robustness of thin-film devices with different layout structures in LTPS technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:12, pp:2067-2073 [Journal]
  33. Kun-Hsien Lin, Ming-Dou Ker
    Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:2-4, pp:301-310 [Journal]
  34. Shih-Hung Chen, Ming-Dou Ker
    Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:7, pp:1042-1049 [Journal]
  35. Ming-Dou Ker, Wei-Jen Chang
    Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:1, pp:27-35 [Journal]
  36. Ming-Dou Ker, Hung-Tai Liao
    Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1121-1124 [Conf]
  37. Zi-Ping Chen, Che-Hao Chuang, Ming-Dou Ker
    Design on new tracking circuit of I/O buffer in 0.13µm cell library for mixed-voltage application. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  38. Bo-Shih Huang, Ming-Dou Ker
    New matching methodology of low-noise amplifier with ESD protection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  39. Ming-Dou Ker, Chien-Hua Wu
    Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  40. Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang
    Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:3, pp:307-321 [Journal]

  41. New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation. [Citation Graph (, )][DBLP]


  42. ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. [Citation Graph (, )][DBLP]


  43. 2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue. [Citation Graph (, )][DBLP]


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