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Kazutami Arimoto: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
    CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5202-5205 [Conf]
  2. Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima
    A New Array Architecture for Parallel Testing in VLSI Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:322-326 [Conf]
  3. Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano
    Test Pattern Considerations for Fault Tolerant High Density DRAM. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:451-455 [Conf]
  4. Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada
    Test cost reduction by at-speed BISR for embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:182-187 [Conf]
  5. Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikishi, Katsunori Suma, Kazuyasu Fujishima
    A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:615-622 [Conf]
  6. Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima
    Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:2, pp:6-12 [Journal]
  7. Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
    Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:525-528 [Conf]

  8. Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. [Citation Graph (, )][DBLP]

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