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Publications of Author

1. Jaeyoung Kwak, Sook Min Park, Kwyro Lee
   Reverse tracing of forward state metric in Log-Map and MAX-Log-MAP decoders. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2003, pp:280-283 [Conf]
   
2. Jaeyoung Kwak, Sook Min Park, Sang-Sic Yoon, Kwyro Lee
   Implementation of a parallel turbo decoder with dividable interleaver. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2003, pp:65-68 [Conf]
   
3. Chang-Ki Kwon, Kwyro Lee
   Reconfigurable and programmable minimum distance search engine for portable video compression systems. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2001, pp:542-545 [Conf]
   
4. Jaeyoung Kwak, Sang-Sic Yoon, Hung-Jun Kwon, Kwyro Lee
   A design of the new FPGA with data path logic and run time block reconfiguration method. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 1999, pp:467-469 [Conf]
   
5. Chang-Ki Kwon, Kwyro Lee
   A low-power minimum distance 1D-search engine using hybrid digital/analog circuit techniques. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 1999, pp:214-217 [Conf]
   
6. Hyung-Chuk Park, Seung-Hyuck Ahn, Young-Jin Kim, Chang-Ki Kwon, Kwyro Lee
   Implementation and performance analysis of programmable test beds for real-time wireless W-CDMA. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 1999, pp:386-389 [Conf]
   
7. Hyung-Joon Kwon, Kwyro Lee
   A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1997, pp:220-224 [Conf]
   
8. Sunil Yu, Dusan Petranovic, Shoba Krishnan, Kwyro Lee, Cary Y. Yang
   Resistance Matrix in Crosstalk Modeling for Muliconductor Systems. [Citation Graph (0, 0)][DBLP]
   ISQED, 2004, pp:122-125 [Conf]
   
9. Kyung-Saeng Kim, KwangMyoung Rho, Kwyro Lee
   Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme. [Citation Graph (0, 0)][DBLP]
   MTDT, 2001, pp:9-12 [Conf]
   
10. Hee-Ran Ahn, Kwyro Lee
    A new measurement technique on inherent-ring-resonance frequency using ring filters. [Citation Graph (0, 0)][DBLP]
    IEICE Electronic Express, 2004, v:1, n:10, pp:269-274 [Journal]
    
11. Kyung-Saeng Kim, Kwyro Lee
    Low-Power 2D Motion Estimation Architecture with Complementary Embedded Memory Banks. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2000, v:10, n:5-6, pp:229-238 [Journal]
    
12. Minkyu Je, Jeonghu Han, Hyungcheol Shin, Kwyro Lee
    A simple four-terminal small-signal model of RF MOSFETs and its parameter extraction. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:4, pp:601-609 [Journal]
    
13. Sangho Shin, Kwyro Lee, Sung-Mo Kang
    2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
14. Sangho Shin, Kwyro Lee, Sung-Mo Kang
    Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
15. Sungchung Park, Kwyro Lee, Sin-Chong Park
    Efficient probabilistic sphere decoding architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
16. Chang-Ki Kwon, Kwyro Lee
    Highly parallel and energy-efficient exhaustive minimum distance search engine using hybrid digital/analog circuit techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:726-729 [Journal]
    
17. Kyung-Saeng Kim, Kwyro Lee
    Low-power and area-efficient FIR filter implementation suitable for multiple taps. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:150-153 [Journal]
    
18. 
    Extrinsic Information Memory Reduced Architecture for Non-Binary Turbo Decoder Implementation. [Citation Graph (, )][DBLP]