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Publications of Author

1. Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu
   Low-power and low-voltage fully parallel content-addressable memory. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:373-376 [Conf]
   
2. Shin-Hong Ou, Chi-Sheng Lin, Bin-Da Liu
   A scalable sorting architecture based on maskable WTA/MAX circuit. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2002, pp:209-212 [Conf]
   
3. Chi-Sheng Lin, Bin-Da Liu
   Design of a pipelined and expandable sorting architecture with simple control scheme. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2002, pp:217-220 [Conf]
   
4. Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu
   A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2004, pp:252-256 [Conf]
   
5. 
   Novel Channel Estimation Techniques in IEEE 802.11p Environments. [Citation Graph (, )][DBLP]
   
   
6. 
   A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. [Citation Graph (, )][DBLP]
   
   
7. 
   Performance evaluations of channel estimations in IEEE 802.11p environments. [Citation Graph (, )][DBLP]