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Seiji Miura: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Seiji Miura, Satoru Akiyama
    A memory controller that reduces latency of cached SDRAM. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5250-5253 [Conf]
  2. Seiji Miura, Kazushige Ayukawa, Takao Watanabe
    A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:358-363 [Conf]

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