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P. V. Ananda Mohan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- P. V. Ananda Mohan
Fast implementations of Montgomery's modular multiplication algorithm. [Citation Graph (0, 0)][DBLP]
ISCAS (4), 2003, pp:125-128 [Conf] - P. V. Ananda Mohan
Novel Design for Binary to RNS Converters. [Citation Graph (0, 0)][DBLP]
ISCAS, 1994, pp:357-360 [Conf] - Y. V. Ramana Rao, P. V. Ananda Mohan
Novel oversampled A/D converters based on error spectrum shaping. [Citation Graph (0, 0)][DBLP]
ISCAS, 1993, pp:212-215 [Conf] - D. V. Poornaiah, P. V. Ananda Mohan
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1995, pp:392-397 [Conf] - D. V. Poornaiah, P. V. Ananda Mohan
A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1996, pp:69-72 [Conf] - P. V. Ananda Mohan
Floating Capacitance Simulation Using Current Conveyors. [Citation Graph (0, 0)][DBLP]
Journal of Circuits, Systems, and Computers, 2005, v:14, n:1, pp:123-128 [Journal] - P. V. Ananda Mohan
Efficient Design of Binary to RNS Converters. [Citation Graph (0, 0)][DBLP]
Journal of Circuits, Systems, and Computers, 1999, v:9, n:3-4, pp:145-154 [Journal]
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