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Tadashi Shibata :
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Tomoyuki Nakayama , Toshihiko Yamasaki , Tadashi Shibata Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2004, pp:425-428 [Conf ] Tomoyuki Nakayama , Toshihiko Yamasaki , Tadashi Shibata A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 2005, pp:5365-5368 [Conf ] Benjamas Tongprasit , Kiyoto Ito , Tadashi Shibata A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2005, pp:2389-2392 [Conf ] Masayuki Umejima , Toshihiko Yamasaki , Tadashi Shibata A bump-circuit-based motion detector using projected-activity histograms. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2004, pp:749-752 [Conf ] Keng Hoong Wee , Toshiyuki Nozawa , T. Yonezawa , Y. Yamashita , Tadashi Shibata , Tadahiro Ohmi High-precision analog EEPROM with real-time write monitoring. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2001, pp:105-108 [Conf ] T. Yamasaki , A. Suzuki , D. Kobayashi , T. Shibata A fast self-convergent flash-memory programming scheme for MV and analog data storage. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2001, pp:930-933 [Conf ] T. Yamasaki , T. Shibata An analog similarity evaluation circuit featuring variable functional forms. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2001, pp:561-564 [Conf ] A. Okada , T. Shibata A neuron-MOS parallel associator for high-speed CDMA matched filter. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 1999, pp:392-395 [Conf ] Hideo Yamasaki , Tadashi Shibata A real-time VLSI median filter employing two-dimensional bit-propagating architecture. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2004, pp:349-352 [Conf ] H. Kimura , T. Shibata A motion-based analog VLSI saliency detector using quasi-two-dimensional hardware algorithm. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2002, pp:333-336 [Conf ] Keng Hoong Wee , T. Yonezawa , Toshiyuki Nozawa , Tadashi Shibata , Tadahiro Ohmi A zone-programmed EEPROM with real-time write monitoring for analog data storage. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2002, pp:655-658 [Conf ] M. Yagi , T. Shibata An associative-processor-based mixed signal system for robust grayscale image recognition. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2002, pp:137-140 [Conf ] T. Yamasaki , T. Taguchi , T. Shibata Low-power CDMA analog matched filters based on floating-gate technology. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2002, pp:625-628 [Conf ] Tadashi Shibata Functional-Device-Based VLSI for Intelligent Electronic Systems. [Citation Graph (0, 0)][DBLP ] ISMVL, 1998, pp:317-0 [Conf ] Yusuke Nakashita , Yoshio Mita , Tadashi Shibata An Analog Visual Pre-Processing Processor. [Citation Graph (0, 0)][DBLP ] NIPS, 2005, pp:- [Conf ] Tadashi Shibata , Koji Kotani , Takeo Yamashita , Hiroshi Ishii , Hideo Kosaka , Tadahiro Ohmi Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors. [Citation Graph (0, 0)][DBLP ] NIPS, 1993, pp:919-926 [Conf ] Tadashi Shibata , Tsutomu Nakai , Tatsuo Morimoto , Ryu Kaihara , Takeo Yamashita , Tadahiro Ohmi Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing. [Citation Graph (0, 0)][DBLP ] NIPS, 1995, pp:685-691 [Conf ] Masakazu Yagi , Hideo Yamasaki , Tadashi Shibata A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors. [Citation Graph (0, 0)][DBLP ] NIPS, 2003, pp:- [Conf ] Toshihiko Yamasaki , Tadashi Shibata Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology. [Citation Graph (0, 0)][DBLP ] NIPS, 2001, pp:1131-1138 [Conf ] Huaiyu Xu , Yoshio Mita , Tadashi Shibata Intelligent Internet Search Applications Based on VLSI Associative Processors. [Citation Graph (0, 0)][DBLP ] SAINT, 2002, pp:230-237 [Conf ] Masakazu Yagi , Tadashi Shibata , Chihiro Tanikawa , Kenji Takada A Robust Medical Image Recognition System Employing Edge-Based Feature Vector Representation. [Citation Graph (0, 0)][DBLP ] SCIA, 2003, pp:534-540 [Conf ] Tadahiro Ohmi , Tadashi Shibata , Koji Kotani , Tsutomu Nakai , Akira Nakada , Ning Mei Yu , Masahiro Konda , Tatsuo Morimoto , Yuichiro Yamashita Association hardware for intelligent electronic systems. [Citation Graph (0, 0)][DBLP ] Systems and Computers in Japan, 1999, v:30, n:12, pp:52-62 [Journal ] K. Ito , T. Shibata A time-domain gradient-detection architecture for VLSI analog motion sensors. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Benjamas Tongprasit , Tadashi Shibata Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] A Low-Power Associative Processor with the R-th Nearest-Match Hamming-Distance Search Engine Employing Time-Domain Techniques. [Citation Graph (, )][DBLP ] A Non-subtraction Configuration of Self-similitude Architecture for Multiple-Resolution Edge-Filtering CMOS Image Sensor. [Citation Graph (, )][DBLP ] Normalized scoring of Hidden Markov Models by on-line learning and its application to gesture-sequence perception. [Citation Graph (, )][DBLP ] An analog self-similitude edge-filtering processor for multiple-resolution image perception. [Citation Graph (, )][DBLP ] Spatiotemporal projection of motion field sequence for generating feature vectors in gesture perception. [Citation Graph (, )][DBLP ] Right brain computing hardware: a psychological brain model on silicon. [Citation Graph (, )][DBLP ] Neuron-MOS continuous-time winner-take-all circuit for intelligent data processing. [Citation Graph (, )][DBLP ] Blind image compression history determination using dynamic thresholding. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.302secs