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Nadia Nedjah: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nadia Nedjah, Luiza de Macedo Mourelle
    Minimal Addition-Subtraction Chains Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ADVIS, 2002, pp:303-313 [Conf]
  2. Nadia Nedjah, Luiza de Macedo Mourelle
    Efficient Parallel Modular Exponentiation Algorithm. [Citation Graph (0, 0)][DBLP]
    ADVIS, 2002, pp:405-414 [Conf]
  3. Nadia Nedjah, Colin D. Walter, Stephen E. Eldridge
    Optimal Left-to-Right Pattern-Matching Automata. [Citation Graph (0, 0)][DBLP]
    ALP/HOA, 1997, pp:273-286 [Conf]
  4. Nadia Nedjah, Luiza de Macedo Mourelle
    More Efficient Left-to-Right Pattern Matching in Non-sequential Equational Programs. [Citation Graph (0, 0)][DBLP]
    CPM, 2003, pp:295-314 [Conf]
  5. Nadia Nedjah, Luiza de Macedo Mourelle
    Massively Parallel Hardware Architecture for Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:231-234 [Conf]
  6. Nadia Nedjah, Luiza de Macedo Mourelle
    Stochastic Reconfigurable Hardware for Neural Networks. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:438-442 [Conf]
  7. Luiza de Macedo Mourelle, Nadia Nedjah
    Fast Reconfigurable Hardware for the M-ary Modular Exponentiation. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:516-523 [Conf]
  8. Nadia Nedjah, Luiza de Macedo Mourelle
    Reconfigurable Hardware Implementation of Montgomery Modular Multiplication and Parallel Binary Exponentiation. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:226-235 [Conf]
  9. Nadia Nedjah
    Postponing Redex Contractions in Equational Programs [Citation Graph (0, 0)][DBLP]
    Fuji International Symposium on Functional and Logic Programming, 1998, pp:40-60 [Conf]
  10. Nadia Nedjah, Luiza de Macedo Mourelle
    Evolutionary State Assignment for Synchronous Finite State Machines. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science, 2004, pp:1289-1296 [Conf]
  11. Luiza de Macedo Mourelle, Nadia Nedjah
    Hardware for Modular Exponentiation Suitable for Smart Cards. [Citation Graph (0, 0)][DBLP]
    ICESS, 2004, pp:196-202 [Conf]
  12. Nadia Nedjah, Luiza de Macedo Mourelle
    Minimal Addition-Subtraction Chains with Ant Colony. [Citation Graph (0, 0)][DBLP]
    ICONIP, 2004, pp:1082-1087 [Conf]
  13. Nadia Nedjah, Luiza de Macedo Mourelle
    Evolvable Hardware Using Genetic Programming. [Citation Graph (0, 0)][DBLP]
    IDEAL, 2003, pp:321-328 [Conf]
  14. Nadia Nedjah, Luiza de Macedo Mourelle
    Minimal Addition-Subtraction Sequences for Efficient Pre-processing in Large Window-Based Modular Exponentiation Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    IDEAL, 2003, pp:329-336 [Conf]
  15. Nadia Nedjah, Luiza de Macedo Mourelle
    Finding Minimal Addition Chains Using Ant Colony. [Citation Graph (0, 0)][DBLP]
    IDEAL, 2004, pp:642-647 [Conf]
  16. Nadia Nedjah, Luiza de Macedo Mourelle
    Improving Space, Time, and Termination in Rewriting-Based Programming. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2001, pp:880-890 [Conf]
  17. Nadia Nedjah, Luiza de Macedo Mourelle
    Minimal Addition Chain for Efficient Modular Exponentiation Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2002, pp:88-98 [Conf]
  18. Nadia Nedjah, Luiza de Macedo Mourelle
    Optimal Adaptive Pattern Matching. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2002, pp:768-779 [Conf]
  19. Nadia Nedjah, Luiza de Macedo Mourelle
    Efficient Pattern Matching for Non-strongly Sequential Term Rewriting Systems. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2003, pp:416-425 [Conf]
  20. Nadia Nedjah, Luiza de Macedo Mourelle
    Efficient Pre-processing for Large Window-Based Modular Exponentiation Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2003, pp:625-635 [Conf]
  21. Nadia Nedjah, Luiza de Macedo Mourelle
    Evolutionary RSA-Based Cryptographic Hardware Using the Co-Design Methodology. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2004, pp:351-360 [Conf]
  22. Nadia Nedjah, Luiza de Macedo Mourelle
    A Comparison of Two Circuit Representations for Evolutionary Digital Circuit Design. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2004, pp:594-604 [Conf]
  23. Nadia Nedjah, Luiza de Macedo Mourelle
    Pareto-Optimal Hardware for Digital Circuits Using SPEA. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2005, pp:534-543 [Conf]
  24. Nadia Nedjah, Luiza de Macedo Mourelle
    Hardware Architecture for Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2005, pp:554-556 [Conf]
  25. Nadia Nedjah, Luiza de Macedo Mourelle
    Fast Hardware of Booth-Barrett?s Modular Multiplication for Efficient Cryptosystems. [Citation Graph (0, 0)][DBLP]
    ISCIS, 2003, pp:27-34 [Conf]
  26. Nadia Nedjah, Luiza de Macedo Mourelle
    Fast Less Recursive Hardware for Large Number Multiplication Using Karatsuba-Ofman's Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCIS, 2003, pp:43-50 [Conf]
  27. Luiza de Macedo Mourelle, Nadia Nedjah
    Efficient Cryptographic Hardware Using the Co-Design Methodology. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:508-512 [Conf]
  28. Luiza de Macedo Mourelle, Nadia Nedjah
    Reconfigurable Hardware for Addition Chains Based Modular Exponentiation. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:603-607 [Conf]
  29. Nadia Nedjah, Luiza de Macedo Mourelle
    Evolutionary Time Scheduling. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:357-361 [Conf]
  30. Nadia Nedjah, Luiza de Macedo Mourelle
    Multi-Objective Evolutionary Hardware for RSA-Based Cryptosystems. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:503-507 [Conf]
  31. Nadia Nedjah, Luiza de Macedo Mourelle
    Pareto-Optimal Hardware for Substitution Boxes. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:614-619 [Conf]
  32. Nadia Nedjah, Luiza de Macedo Mourelle
    Four Hardware Implementations for the M-ary Modular Exponentiation. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:210-215 [Conf]
  33. Nadia Nedjah, Luiza de Macedo Mourelle, Marco Paulo Cardoso
    A Compact Piplined Hardware Implementation of the AES-128 Cipher. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:216-221 [Conf]
  34. Nadia Nedjah, Luiza de Macedo Mourelle, Rodrigo Martins da Silva
    Efficient Hardware for Modular Exponentiation Using the Sliding-Window Method. [Citation Graph (0, 0)][DBLP]
    ITNG, 2007, pp:17-24 [Conf]
  35. Nadia Nedjah, Luiza de Macedo Mourelle
    Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron. [Citation Graph (0, 0)][DBLP]
    IWANN (2), 2003, pp:17-24 [Conf]
  36. Nadia Nedjah, Luiza de Macedo Mourelle
    Efficient Pre-processing for Large Window-Based Modular Exponentiation Using Ant Colony. [Citation Graph (0, 0)][DBLP]
    KES (4), 2005, pp:640-646 [Conf]
  37. Nadia Nedjah, Luiza de Macedo Mourelle
    How Many CLBs Does Your Circuit Need to be Implemented?. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:174-181 [Conf]
  38. Nadia Nedjah, Luiza de Macedo Mourelle
    Three Hardware Implementations for the Binary Modular Exponentiation: Sequential, Parallel and Systolic. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2003, pp:246-253 [Conf]
  39. Nadia Nedjah, Luiza de Macedo Mourelle
    FPGA-Based Hardware Architecture for Neural Networks: Binary Radix vs. Stochastic. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:111-0 [Conf]
  40. Nadia Nedjah, Luiza de Macedo Mourelle
    Efficient Hardware Implementation of Modular Multiplication and Exponentiation for Public-Key Cryptography. [Citation Graph (0, 0)][DBLP]
    VECPAR, 2002, pp:451-463 [Conf]
  41. Nadia Nedjah, Luiza de Macedo Mourelle
    Complete Pattern Matching: Recursivity Versus Multi-threading. [Citation Graph (0, 0)][DBLP]
    VECPAR, 2004, pp:598-609 [Conf]
  42. Nadia Nedjah, Luiza de Macedo Mourelle
    Minimal Adaptive Pattern-Matching Automata for Efficient Term Rewriting. [Citation Graph (0, 0)][DBLP]
    CIAA, 2001, pp:221-233 [Conf]
  43. Nadia Nedjah, Luiza de Macedo Mourelle
    Pattern Matching Code Minimization in Rewriting-Based Programming Languages. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2002, v:13, n:6, pp:873-887 [Journal]
  44. Nadia Nedjah, Luiza de Macedo Mourelle
    Efficient Pre-Processing for Large Window-Based Modular Exponentiation Using Ant Colony. [Citation Graph (0, 0)][DBLP]
    Informatica (Slovenia), 2005, v:29, n:2, pp:155-162 [Journal]
  45. Nadia Nedjah, Luiza de Macedo Mourelle
    Multi-Objective CMOS-Targeted Evolutionary Hardware for Combinational Digital Circuits. [Citation Graph (0, 0)][DBLP]
    Informatica (Slovenia), 2005, v:29, n:3, pp:309-320 [Journal]
  46. Nadia Nedjah, Luiza de Macedo Mourelle
    Embedded cryptographic hardware. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:1, pp:1-2 [Journal]
  47. Nadia Nedjah, Luiza de Macedo Mourelle
    Efficient and secure cryptographic systems based on addition chains: Hardware design vs. software/hardware co-design. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:1, pp:36-44 [Journal]
  48. Nadia Nedjah, Luiza de Macedo Mourelle
    More efficient left-to-right matching for overlapping pattern. [Citation Graph (0, 0)][DBLP]
    J. Discrete Algorithms, 2005, v:3, n:2-4, pp:230-247 [Journal]
  49. Nadia Nedjah, Luiza de Macedo Mourelle
    Embedded cryptographic hardware. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:2-3, pp:69-71 [Journal]
  50. Nadia Nedjah, Luiza de Macedo Mourelle
    Fast hardware for modular exponentiation with efficient exponent pre-processing. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:2-3, pp:99-108 [Journal]
  51. Nadia Nedjah, Luiza de Macedo Mourelle
    Fast reconfigurable systolic hardware for modular multiplication and exponentiation. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:7-9, pp:387-396 [Journal]
  52. Nadia Nedjah, Luiza de Macedo Mourelle
    Software/Hardware Co-Design of Efficient and Secure Cryptographic Hardware. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2005, v:11, n:1, pp:66-82 [Journal]
  53. Nadia Nedjah, Luiza de Macedo Mourelle
    Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2006, v:12, n:4, pp:367-369 [Journal]
  54. Nadia Nedjah, Luiza de Macedo Mourelle
    Pareto-Optimal Hardware for Substitution Boxes. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2006, v:12, n:4, pp:395-407 [Journal]
  55. Nadia Nedjah, Luiza de Macedo Mourelle
    Efficient Concise Deterministic Pattern-Matching Automata for Ambiguous Patterns. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Notices, 2002, v:37, n:2, pp:57-67 [Journal]
  56. Nadia Nedjah
    Minimal Deterministic Left-to-Right Pattern-Matching Automata. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Notices, 1998, v:33, n:1, pp:40-47 [Journal]
  57. Nadia Nedjah, Colin D. Walter, Stephen E. Eldridge
    Efficient Automata-Driven Pattern-Matching for Equational Programs. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1999, v:29, n:9, pp:793-813 [Journal]
  58. Nadia Nedjah, Luiza de Macedo Mourelle
    Dynamic deterministic pattern-matching. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2000, v:31, n:, pp:- [Journal]
  59. Nadia Nedjah, Luiza de Macedo Mourelle
    Evolutionary Design of Resilient Substitution Boxes: From Coding to Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    ICES, 2007, pp:403-414 [Conf]
  60. Nadia Nedjah, Luiza de Macedo Mourelle
    A Versatile Pipelined Hardware Implementation for Encryption and Decryption Using Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    VECPAR, 2006, pp:249-259 [Conf]
  61. Nadia Nedjah, Luiza de Macedo Mourelle
    AST Pre-Processing For The Sliding Window Method Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    Int. J. Comput. Syst. Signal, 2003, v:4, n:2, pp:11- [Journal]
  62. Nadia Nedjah, Luiza de Macedo Mourelle
    Evolving Optimal Multi-Objective Hardware Using Strength Pareto Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    Int. J. Comput. Syst. Signal, 2005, v:6, n:1, pp:37-47 [Journal]
  63. Nadia Nedjah, Luiza de Macedo Mourelle
    Special Issue On Multi-Objective Evolution: Editorial. [Citation Graph (0, 0)][DBLP]
    Int. J. Comput. Syst. Signal, 2005, v:6, n:1, pp:1-2 [Journal]
  64. Nadia Nedjah, Luiza de Macedo Mourelle
    Dedicated hardware architectures for intelligent systems. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2007, v:71, n:1-3, pp:1-2 [Journal]
  65. Nadia Nedjah, Luiza de Macedo Mourelle
    An efficient problem-independent hardware implementation of genetic algorithms. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2007, v:71, n:1-3, pp:88-94 [Journal]
  66. Nadia Nedjah, Ajith Abraham, Luiza de Macedo Mourelle
    Hybrid artificial neural network. [Citation Graph (0, 0)][DBLP]
    Neural Computing and Applications, 2007, v:16, n:3, pp:207-208 [Journal]
  67. Nadia Nedjah, Luiza de Macedo Mourelle
    Reconfigurable hardware for neural networks: binary versus stochastic. [Citation Graph (0, 0)][DBLP]
    Neural Computing and Applications, 2007, v:16, n:3, pp:249-255 [Journal]

  68. A Hardware/Software Co-design vs. Hardware Implementation of the Modular Exponentiation Using the Sliding-Window Method with Constant-Length Partitioning. [Citation Graph (, )][DBLP]


  69. GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids. [Citation Graph (, )][DBLP]


  70. A Massively Parallel Hardware for Modular Exponentiations Using the m-ary Method. [Citation Graph (, )][DBLP]


  71. Automatic Modeling of Fuzzy Systems Using Particle Swarm Optimization. [Citation Graph (, )][DBLP]


  72. Reconfigurable MAC-Based Architecture for Parallel Hardware Implementation on FPGAs of Artificial Neural Networks. [Citation Graph (, )][DBLP]


  73. Reconfigurable MAC-Based Architecture for Parallel Hardware Implementation on FPGAs of Artificial Neural Networks Using Fractional Fixed Point Representation. [Citation Graph (, )][DBLP]


  74. Optimised State Assignment for FSMs Using Quantum Inspired Evolutionary Algorithm. [Citation Graph (, )][DBLP]


  75. Logic Synthesis for FSMs Using Quantum Inspired Evolution. [Citation Graph (, )][DBLP]


  76. Evolutionary Public-Key Cryptographic Circuits. [Citation Graph (, )][DBLP]


  77. Application Synthesis for MPSoCs Implementation Using Multiobjective Optimization. [Citation Graph (, )][DBLP]


  78. Efficient Hardware for Modular Exponentiation Using the Sliding-Window Method with Variable-Length Partitioning. [Citation Graph (, )][DBLP]


  79. SoC-based implementation for modular exponentiation using evolutionary addition chains. [Citation Graph (, )][DBLP]


  80. Evolutionary IP assignment for efficient NoC-based system design using multi-objective optimization. [Citation Graph (, )][DBLP]


  81. A System-on-Chip Implementation for Modular Exponentiation Using the Sliding-Window Method with Variable-Length Partitioning. [Citation Graph (, )][DBLP]


  82. Towards Very Fast Modular Exponentiations Using Ant Colony. [Citation Graph (, )][DBLP]


  83. Efficient Hardware for Modular Exponentiation using the Sliding-Window Method with Variable-Length Partitioning. [Citation Graph (, )][DBLP]


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