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Arun Ravindran:
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- Arun Ravindran, Anup Savla, Jennifer Leonard
Digital error correction and calibration of gain non-linearities in a pipelined ADC. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2004, pp:1-4 [Conf]
- Anup Savla, Jennifer Leonard, Arun Ravindran
A novel queuing architecture for background calibration of pipeline ADCs. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2004, pp:65-68 [Conf]
- Seoung-Jae Yoo, Arun Ravindran, Mohammed Ismail
A low voltage CMOS transresistance-based variable gain amplifier. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2004, pp:809-812 [Conf]
- Anup Savla, Jennifer Leonard, Arun Ravindran
Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration. [Citation Graph (0, 0)][DBLP] VLSI Design, 2004, pp:157-162 [Conf]
- Daniel Davids, Siddhartha Datta, Arindam Mukherjee, Bharat Joshi, Arun Ravindran
Multiple fault diagnosis in digital microfluidic biochips. [Citation Graph (0, 0)][DBLP] JETC, 2006, v:2, n:4, pp:262-276 [Journal]
- Kushal Datta, Arindam Mukherjee, Arun Ravindran
Automated design flow for diode-based nanofabrics. [Citation Graph (0, 0)][DBLP] JETC, 2006, v:2, n:3, pp:219-241 [Journal]
- Srikanth Mohan, Arun Ravindran, David Binkley, Arindam Mukherjee
Power Optimized Design of CMOS Programmable Gain Amplifiers. [Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2006, v:2, n:2, pp:259-270 [Journal]
- Steven D. Tucker, Arun Ravindran, Christopher Wichman, Arindam Mukherjee
Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2007, v:3, n:1, pp:60-69 [Journal]
Reduced dimensional HRTF processing for gaming environments. [Citation Graph (, )][DBLP]
A multi-threaded DNA tag/anti-tag library generator for multi-core platforms. [Citation Graph (, )][DBLP]
Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer. [Citation Graph (, )][DBLP]
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