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Arun Ravindran: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Arun Ravindran, Anup Savla, Jennifer Leonard
    Digital error correction and calibration of gain non-linearities in a pipelined ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:1-4 [Conf]
  2. Anup Savla, Jennifer Leonard, Arun Ravindran
    A novel queuing architecture for background calibration of pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:65-68 [Conf]
  3. Seoung-Jae Yoo, Arun Ravindran, Mohammed Ismail
    A low voltage CMOS transresistance-based variable gain amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:809-812 [Conf]
  4. Anup Savla, Jennifer Leonard, Arun Ravindran
    Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:157-162 [Conf]
  5. Daniel Davids, Siddhartha Datta, Arindam Mukherjee, Bharat Joshi, Arun Ravindran
    Multiple fault diagnosis in digital microfluidic biochips. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:4, pp:262-276 [Journal]
  6. Kushal Datta, Arindam Mukherjee, Arun Ravindran
    Automated design flow for diode-based nanofabrics. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:3, pp:219-241 [Journal]
  7. Srikanth Mohan, Arun Ravindran, David Binkley, Arindam Mukherjee
    Power Optimized Design of CMOS Programmable Gain Amplifiers. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:259-270 [Journal]
  8. Steven D. Tucker, Arun Ravindran, Christopher Wichman, Arindam Mukherjee
    Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:60-69 [Journal]

  9. Reduced dimensional HRTF processing for gaming environments. [Citation Graph (, )][DBLP]


  10. A multi-threaded DNA tag/anti-tag library generator for multi-core platforms. [Citation Graph (, )][DBLP]


  11. Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer. [Citation Graph (, )][DBLP]


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