The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Sai-Weng Sin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca
    Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:129-132 [Conf]
  2. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:369-372 [Conf]
  3. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1585-1588 [Conf]
  4. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1581-1584 [Conf]
  5. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  6. Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
    A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  7. A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. [Citation Graph (, )][DBLP]


Search in 0.017secs, Finished in 0.018secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002