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Mindaugas Drazdziulis:
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- Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson
A low-leakage twin-precision multiplier using reconfigurable power gating. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2005, pp:1654-1657 [Conf]
- Mindaugas Drazdziulis, Per Larsson-Edefors
Evaluation of power cut-off techniques in the presence of gate leakage. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:745-748 [Conf]
- Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. [Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:557-563 [Conf]
- Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. [Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:185-191 [Conf]
- Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson
Overdrive Power-Gating Techniques for Total Power Minimization. [Citation Graph (0, 0)][DBLP] ISVLSI, 2007, pp:125-132 [Conf]
High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. [Citation Graph (, )][DBLP]
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