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James H. Mulligan Jr.: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
Integration of Clock Skew and Register Delays into a Retiming Algorithm. [Citation Graph (0, 0)][DBLP]
ISCAS, 1993, pp:1483-1486 [Conf] - Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. [Citation Graph (0, 0)][DBLP]
ISCAS, 1995, pp:1748-1751 [Conf] - Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
Incorporating interconnect, register, and clock distribution delays into the retiming process. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:105-120 [Journal]
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