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Henrik Svensson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Henrik Svensson, Viktor Öwall, Krzysztof Kuchcinski
    Implementation aspects of a novel speech packet loss concealment method. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2867-2870 [Conf]
  2. Hugo Hedberg, Thomas Lenart, Henrik Svensson
    A Complete MP3 Decoder on a Chip. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:103-104 [Conf]
  3. Hugo Hedberg, Thomas Lenart, Henrik Svensson, Peter Nilsson, Viktor Öwall
    Teaching Digital HW-Design by Implementing a Complete MP3 Decoder. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:31-32 [Conf]
  4. Hugo Hedberg, Joachim Neves Rodrigues, Fredrik Kristensen, Henrik Svensson, Matthias Kamuf, Viktor Öwall
    Teaching Digital ASIC Design to Students with Heterogeneous Previous Knowledge. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:15-16 [Conf]
  5. Tom Ziemke, Nicklas Bergfeldt, Gunnar Búason, Tarja Susi, Henrik Svensson
    Evolving cognitive scaffolding and environment adaptation: a new research direction for evolutionary robotics. [Citation Graph (0, 0)][DBLP]
    Connect. Sci., 2004, v:16, n:4, pp:339-350 [Journal]
  6. Henrik Svensson, Thomas Lenart, Viktor Öwall
    Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3972-3975 [Conf]

  7. A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing. [Citation Graph (, )][DBLP]


  8. Implementing the G.723.1 Speech Codec Using a Coarse-Grained Reconfigurable Coprocessor. [Citation Graph (, )][DBLP]


  9. Modelling and exploration of a reconfigurable array using systemC TLM. [Citation Graph (, )][DBLP]


  10. Modeling and exploration of a reconfigurable architecture for digital holographic imaging. [Citation Graph (, )][DBLP]


  11. Neural Pathways of Embodied Simulation. [Citation Graph (, )][DBLP]


  12. Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications. [Citation Graph (, )][DBLP]


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