The SCEAS System
| |||||||

## Search the dblp DataBase
Okihiko Ishizuka:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- Zheng Tang, Yuichi Shirata, Okihiko Ishizuka, Koichi Tanno
**A Self-Calibrating A/D Converter Using T-Model Neural Network.**[Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:533-536 [Conf] - Qi-xin Cao, Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto
**Algorithm and Implementation of a Learning Multiple-Valued Logic Network.**[Citation Graph (0, 0)][DBLP] ISMVL, 1993, pp:202-207 [Conf] - Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
**Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators.**[Citation Graph (0, 0)][DBLP] ISMVL, 2001, pp:27-0 [Conf] - Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
**Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits.**[Citation Graph (0, 0)][DBLP] ISMVL, 2002, pp:282-0 [Conf] - Okihiko Ishizuka, Hiroshi Takarabe, Zheng Tang, Hiroki Matsumoto
**Synthesis of Current-Mode Pass Transistor Networks.**[Citation Graph (0, 0)][DBLP] ISMVL, 1991, pp:139-146 [Conf] - Okihiko Ishizuka, Akihiro Ohta, Koichi Tanno, Zheng Tang, Dwi Handoko
**VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products.**[Citation Graph (0, 0)][DBLP] ISMVL, 1997, pp:169-174 [Conf] - Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto
**On Design of Multiple-Valued Static Random-Access-Memory.**[Citation Graph (0, 0)][DBLP] ISMVL, 1990, pp:11-17 [Conf] - Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
**Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors.**[Citation Graph (0, 0)][DBLP] ISMVL, 2000, pp:15-20 [Conf] - Jing Shen, Koichi Tanno, Okihiko Ishizuka
**Down Literal Circuit with Neuron-MOS Transistors and Its Applications.**[Citation Graph (0, 0)][DBLP] ISMVL, 1999, pp:180-185 [Conf] - Jing Shen, Koichi Tanno, Okihiko Ishizuka, Zheng Tang
**Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits.**[Citation Graph (0, 0)][DBLP] ISMVL, 1998, pp:128-133 [Conf] - Zheng Tang, Okihiko Ishizuka, Qi-xin Cao, Hiroki Matsumoto
**Algebraic Properties of a Learning Multiple-Valued Logic Network.**[Citation Graph (0, 0)][DBLP] ISMVL, 1993, pp:196-201 [Conf] - Zheng Tang, Okihiko Ishizuka, Koichi Tanno
**Learning Multiple-Valued Logic Networks Based on Back Propagation.**[Citation Graph (0, 0)][DBLP] ISMVL, 1995, pp:270-275 [Conf] - Zheng Tang, T. Yamaguchi, Koichi Tashima, Okihiko Ishizuka, Koichi Tanno
**Multiple-Valued Immune Network Model and Its Simulations.**[Citation Graph (0, 0)][DBLP] ISMVL, 1997, pp:233-0 [Conf] - Makoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka
**Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions.**[Citation Graph (0, 0)][DBLP] ISMVL, 2000, pp:27-32 [Conf] - Koichi Tashima, Zheng Tang, Okihiko Ishizuka, Koichi Tanno
**An immune network with interactions between B cells for pattern recognition.**[Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 2001, v:32, n:10, pp:31-41 [Journal] - Okihiko Ishizuka
**On Multivalued Multithreshold Networks Composed of Conventional Threshold Elements.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1977, v:26, n:12, pp:1251-1257 [Journal] - Zheng Tang, Okihiko Ishizuka
**A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1998, v:47, n:2, pp:247-251 [Journal]
Search in 0.002secs, Finished in 0.003secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |