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Publications of Author

1. Zheng Tang, Yuichi Shirata, Okihiko Ishizuka, Koichi Tanno
   A Self-Calibrating A/D Converter Using T-Model Neural Network. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:533-536 [Conf]
   
2. Qi-xin Cao, Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto
   Algorithm and Implementation of a Learning Multiple-Valued Logic Network. [Citation Graph (0, 0)][DBLP]
   ISMVL, 1993, pp:202-207 [Conf]
   
3. Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
   Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2001, pp:27-0 [Conf]
   
4. Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
   Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2002, pp:282-0 [Conf]
   
5. Okihiko Ishizuka, Hiroshi Takarabe, Zheng Tang, Hiroki Matsumoto
   Synthesis of Current-Mode Pass Transistor Networks. [Citation Graph (0, 0)][DBLP]
   ISMVL, 1991, pp:139-146 [Conf]
   
6. Okihiko Ishizuka, Akihiro Ohta, Koichi Tanno, Zheng Tang, Dwi Handoko
   VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products. [Citation Graph (0, 0)][DBLP]
   ISMVL, 1997, pp:169-174 [Conf]
   
7. Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto
   On Design of Multiple-Valued Static Random-Access-Memory. [Citation Graph (0, 0)][DBLP]
   ISMVL, 1990, pp:11-17 [Conf]
   
8. Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
   Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2000, pp:15-20 [Conf]
   
9. Jing Shen, Koichi Tanno, Okihiko Ishizuka
   Down Literal Circuit with Neuron-MOS Transistors and Its Applications. [Citation Graph (0, 0)][DBLP]
   ISMVL, 1999, pp:180-185 [Conf]
   
10. Jing Shen, Koichi Tanno, Okihiko Ishizuka, Zheng Tang
    Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:128-133 [Conf]
    
11. Zheng Tang, Okihiko Ishizuka, Qi-xin Cao, Hiroki Matsumoto
    Algebraic Properties of a Learning Multiple-Valued Logic Network. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:196-201 [Conf]
    
12. Zheng Tang, Okihiko Ishizuka, Koichi Tanno
    Learning Multiple-Valued Logic Networks Based on Back Propagation. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:270-275 [Conf]
    
13. Zheng Tang, T. Yamaguchi, Koichi Tashima, Okihiko Ishizuka, Koichi Tanno
    Multiple-Valued Immune Network Model and Its Simulations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:233-0 [Conf]
    
14. Makoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka
    Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:27-32 [Conf]
    
15. Koichi Tashima, Zheng Tang, Okihiko Ishizuka, Koichi Tanno
    An immune network with interactions between B cells for pattern recognition. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2001, v:32, n:10, pp:31-41 [Journal]
    
16. Okihiko Ishizuka
    On Multivalued Multithreshold Networks Composed of Conventional Threshold Elements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:12, pp:1251-1257 [Journal]
    
17. Zheng Tang, Okihiko Ishizuka
    A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:2, pp:247-251 [Journal]