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Zhongfeng Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhongfeng Wang, Qing-wei Jia
    Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5786-5789 [Conf]
  2. Zhongfeng Wang, Yiyan Tang, Yuke Wang
    Low hardware complexity parallel turbo decoder architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:53-56 [Conf]
  3. Tong Zhang, Zhongfeng Wang, Keshab K. Parhi
    On finite precision implementation of low density parity check codes decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:202-205 [Conf]
  4. S. Summerfield, Zhongfeng Wang, Keshab K. Parhi
    Area-power-time efficient pipeline-interleaved architectures for wave digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 1999, pp:343-346 [Conf]
  5. Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi
    On the better protection of short-frame turbo codes. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Communications, 2004, v:52, n:9, pp:1435-1439 [Journal]
  6. Zhongfeng Wang, Jun Ma
    High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:937-950 [Journal]
  7. Jun Ma, Alexander Vardy, Zhongfeng Wang, Qinqin Chen
    Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1409-1412 [Conf]
  8. Qinqin Chen, Zhongfeng Wang, Jun Ma
    FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2100-2103 [Conf]
  9. Zhiqiang Cui, Zhongfeng Wang
    Efficient Message Passing Architecture for High Throughput LDPC Decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:917-920 [Conf]
  10. Qingwei Li, Zhongfeng Wang
    Improved k-best sphere decoding algorithms for MIMO systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  11. Jun Ma, Alexander Vardy, Zhongfeng Wang
    Reencoder design for soft-decision decoding of an (255, 239) Reed-Solomon code. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  12. Jun Ma, Alexander Vardy, Zhongfeng Wang
    Efficient fast interpolation architecture for soft-decision decoding of Reed-Solomon codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  13. Zhiqiang Cui, Zhongfeng Wang
    A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  14. Zhiqiang Cui, Zhongfeng Wang
    Area-efficient parallel decoder architecture for high rate QC-LDPC codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  15. Zhongfeng Wang, Zhiqiang Cui
    Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:104-114 [Journal]
  16. Jun Ma, Alexander Vardy, Zhongfeng Wang
    Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1225-1238 [Journal]
  17. Zhongfeng Wang, Zhiqiang Cui
    A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:483-488 [Journal]
  18. Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi
    Area-efficient high-speed decoding schemes for turbo decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:902-912 [Journal]

  19. An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems. [Citation Graph (, )][DBLP]


  20. Extended layered decoding of LDPC codes. [Citation Graph (, )][DBLP]


  21. Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes. [Citation Graph (, )][DBLP]


  22. A low-complexity high-performance noncoherent receiver for GFSK signals. [Citation Graph (, )][DBLP]


  23. Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes. [Citation Graph (, )][DBLP]


  24. An FPGA Implementation of Array LDPC Decoder. [Citation Graph (, )][DBLP]


  25. Fast EBCOT Encoder Architecture for JPEG 2000. [Citation Graph (, )][DBLP]


  26. Studies on Practical Low Complexity Decoding of Low-Density Parity-Check Codes. [Citation Graph (, )][DBLP]


  27. Design of Low-Power Memory-Efficient Viterbi Decoder. [Citation Graph (, )][DBLP]


  28. Early-Pruning K-Best Sphere Decoder for MIMO Systems. [Citation Graph (, )][DBLP]


  29. Error correction for multi-level NAND flash memory using Reed-Solomon codes. [Citation Graph (, )][DBLP]


  30. Low-complexity high-speed 4-D TCM decoder. [Citation Graph (, )][DBLP]


  31. An improved min-sum based column-layered decoding algorithm for LDPC codes. [Citation Graph (, )][DBLP]


  32. High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications. [Citation Graph (, )][DBLP]


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