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Publications of Author

1. Jin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu
   Probabilistic congestion prediction in hierarchical quad-grid model. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2005, pp:1350-1353 [Conf]
   
2. Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen
   Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. [Citation Graph (0, 0)][DBLP]
   ISCAS (3), 2005, pp:2219-2222 [Conf]
   
3. Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen
   Wiring area optimization in floorplan-aware hierarchical power grids. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2005, pp:1366-1369 [Conf]
   
4. Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen
   Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:147-152 [Conf]
   
5. Jin-Tai Yan, Kuen-Ming Lin, Yen-Hsiang Chen
   Optimal shielding insertion for inductive noise avoidance. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
6. Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang
   Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
7. 
   Integrating Bi-Direction Audio and Video Transmission for UltraVNC. [Citation Graph (, )][DBLP]