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Hsie-Chia Chang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hsie-Chia Chang, Chen-Yi Lee
    An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:649-652 [Conf]
  2. Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang
    Multi-level memory systems using error control codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:393-396 [Conf]
  3. Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
    A power and area efficient multi-mode FEC processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:253-256 [Conf]
  4. Hsie-Chia Chang, Chen-Yi Lee
    A Low-Power Design for Reed-Solomon Decoders. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:2, pp:159-170 [Journal]
  5. Chien-Ching Lin, Y.-H. Shih, Hsie-Chia Chang, Chen-Yi Lee
    A low power turbo/Viterbi decoder for 3GPP2 applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:426-430 [Journal]
  6. Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang
    A self-compensation fixed-width booth multiplier and its 128-point FFT applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  7. Early-Pruned K-Best Sphere Decoding Algorithm Based on Radius Constraints. [Citation Graph (, )][DBLP]


  8. Structured LDPCcodes with low error floor based on PEG tanner graphs. [Citation Graph (, )][DBLP]


  9. Multi-mode message passing switch networks applied for QC-LDPC decoder. [Citation Graph (, )][DBLP]


  10. Low-complexity Prediction Techniques of K-best Sphere Decoding for MIMO Systems. [Citation Graph (, )][DBLP]


  11. Carry Estimation for Two's Complement Fixed-Width Multipliers. [Citation Graph (, )][DBLP]


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