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Publications of Author

1. C. Chakrabarti, D. Gaitonde
   Instruction level power model of microcontrollers. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 1999, pp:76-79 [Conf]
   
2. C. Chakrabarti
   A DWT-based encoder architecture for symmetrically extended images. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 1999, pp:123-126 [Conf]
   
3. S. H. Tadas, C. Chakrabarti
   Architectural approaches to reduce leakage energy in caches. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2002, pp:481-484 [Conf]
   
4. P. Chowdhury, C. Chakrabarti
   Static task-scheduling algorithms for battery-powered DVS systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:226-237 [Journal]
   
5. J. Kaza, C. Chakrabarti
   Design and implementation of low-energy turbo decoders. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:968-977 [Journal]
   
6. M. Tiwari, Yuming Zhu, C. Chakrabarti
   Memory sub-banking scheme for high throughput MAP-based SISO decoders. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:494-498 [Journal]
   
7. Yuming Zhu, L. Li, C. Chakrabarti
   Study of energy and performance of space-time decoding systems in concatenation with turbo decoding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:86-90 [Journal]
   
8. C. Chakrabarti, C. Mumford
   Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:289-298 [Journal]
   
9. A. Manzak, C. Chakrabarti
   A low power scheduling scheme with resources operating at multiple voltages. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:6-14 [Journal]