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Bhaskar Chatterjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Christine Kwong, Bhaskar Chatterjee, Manoj Sachdev
    Modeling and designing energy-delay optimized wide domino circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:921-924 [Conf]
  2. Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
    Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:122-127 [Conf]
  3. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
    A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:248-251 [Conf]
  4. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
    Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:415-420 [Conf]
  5. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1130-1139 [Conf]
  6. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1108-1117 [Conf]
  7. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    DFT for Delay Fault Testing of High-Performance Digital Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:248-258 [Journal]
  8. Bhaskar Chatterjee, Manoj Sachdev
    Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1296-1304 [Journal]
  9. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
    Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:9, pp:801-809 [Journal]

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