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Chien-Ching Lin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang
    Multi-level memory systems using error control codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:393-396 [Conf]
  2. Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
    A power and area efficient multi-mode FEC processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:253-256 [Conf]
  3. Chien-Ching Lin, Y.-H. Shih, Hsie-Chia Chang, Chen-Yi Lee
    A low power turbo/Viterbi decoder for 3GPP2 applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:426-430 [Journal]

  4. Multi-mode message passing switch networks applied for QC-LDPC decoder. [Citation Graph (, )][DBLP]

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