Search the dblp DataBase
Soo Hwan Kim :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Ge Yang , Seong-Ook Jung , Kwang-Hyun Baek , Soo Hwan Kim , Suki Kim , Sung-Mo Kang A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2004, pp:781-784 [Conf ] Yong Sin Kim , Soo Hwan Kim , Kwang-Hyun Baek , Suki Kim , Sung-Mo Kang Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2003, pp:261-0 [Conf ] Ge Yang , Seong-Ook Jung , Kwang-Hyun Baek , Soo Hwan Kim , Suki Kim , Sung-Mo Kang A 32-bit carry lookahead adder using dual-path all-N logic. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:992-996 [Journal ] Jae Ug Jeong , Soo Hwan Kim Weak and strong convergence of the Ishikawa iteration process with errors for two asymptotically nonexpansive mappings. [Citation Graph (0, 0)][DBLP ] Applied Mathematics and Computation, 2006, v:181, n:2, pp:1394-1401 [Journal ] Youngkwon Jo , Yong Shim , Soo Hwan Kim , Suki Kim , Kwanjun Cho A mixed-structure delay locked-loop with wide range and fast locking. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Yong Shim , Youngkwon Jo , Soo Hwan Kim , Suki Kim , Kwanjun Cho A register controlled delay locked loop using a TDC and a new fine delay line scheme. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Search in 0.001secs, Finished in 0.001secs