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Anne E. Gattiker: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long
    Static timing analysis based circuit-limited-yield estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:81-84 [Conf]
  2. Anne E. Gattiker
    IC failure mechanisms yesterday, today, tomorrow: implications from test to DFM. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:47- [Conf]
  3. Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long
    Timing Yield Estimation from Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:437-442 [Conf]
  4. Anne E. Gattiker
    Diagnosis Meets Physical Failure Analysis: How Long can we Succeed? [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1441- [Conf]
  5. Anne E. Gattiker, Wojciech Maly
    Feasibility Study of Smart Substrate Multichip Modules. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:41-49 [Conf]
  6. Anne E. Gattiker, Wojciech Maly
    Current Signatures: Application. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:156-165 [Conf]
  7. Anne E. Gattiker, Wojciech Maly
    Current signatures: application [to CMOS]. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:1168-1177 [Conf]
  8. Anne E. Gattiker, Wojciech Maly
    Toward understanding "Iddq-only" fails. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:174-183 [Conf]
  9. Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey
    Deformations of IC Structure in Test and Yield Learning. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:856-865 [Conf]
  10. Phil Nigh, Anne E. Gattiker
    Test method evaluation experiments and data. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:454-463 [Conf]
  11. Phil Nigh, Anne E. Gattiker
    Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:309-318 [Conf]
  12. Abhishek Singh, Chintan Patel, Shirong Liao, James F. Plusquellic, Anne E. Gattiker
    Detecting delay faults using power supply transient signal analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:395-404 [Conf]
  13. Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly
    To DFT or Not to DFT? [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:557-566 [Conf]
  14. Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu
    Test structures for delay variability. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:109- [Conf]
  15. Anne E. Gattiker, Wojciech Maly
    Current signatures [VLSI circuit testing]. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:112-117 [Conf]
  16. Abhishek Singh, Jim Plusquellic, Anne E. Gattiker
    Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:357-366 [Conf]
  17. Anne E. Gattiker
    Getting More out of ITC. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:432- [Journal]
  18. Wojciech Maly, Derek Feltham, Anne E. Gattiker, Mark D. Hobaugh, Kenneth Backus, Michael E. Thomas
    Smart-Substrate Multichip-Module Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:2, pp:64-73 [Journal]
  19. Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly
    Modeling the Economics of Testing: A DFT Perspective. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:1, pp:29-41 [Journal]
  20. James F. Plusquellic, Abhishek Singh, Chintan Patel, Anne E. Gattiker
    Power supply transient signal analysis for defect-oriented test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:370-374 [Journal]

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