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Publications of Author

1. Akashi Satoh, Nobuyuki Ooba, Kohji Takano, Edward D'Avignon
   High-Speed MARS Hardware. [Citation Graph (0, 0)][DBLP]
   AES Candidate Conference, 2000, pp:305-316 [Conf]
   
2. Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh
   A Compact Rijndael Hardware Architecture with S-Box Optimization. [Citation Graph (0, 0)][DBLP]
   ASIACRYPT, 2001, pp:239-254 [Conf]
   
3. Sumio Morioka, Akashi Satoh
   An Optimized S-Box Circuit Architecture for Low Power AES Design. [Citation Graph (0, 0)][DBLP]
   CHES, 2002, pp:172-186 [Conf]
   
4. Akashi Satoh, Sumio Morioka
   Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. [Citation Graph (0, 0)][DBLP]
   CHES, 2003, pp:304-318 [Conf]
   
5. Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh
   High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. [Citation Graph (0, 0)][DBLP]
   CHES, 2006, pp:187-200 [Conf]
   
6. W. K. Luk, Y. Katayama, Wei Hwang, M. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
   Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. [Citation Graph (0, 0)][DBLP]
   ICCD, 1997, pp:279-285 [Conf]
   
7. Sumio Morioka, Akashi Satoh
   A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. [Citation Graph (0, 0)][DBLP]
   ICCD, 2002, pp:98-103 [Conf]
   
8. Akashi Satoh, Y. Kobayashi, H. Niijima, Nobuyuki Ooba, Seiji Munetoh, S. Sone
   A High-Speed Small RSA Encryption LSI with Low Power Dissipation. [Citation Graph (0, 0)][DBLP]
   ISW, 1997, pp:174-187 [Conf]
   
9. Akashi Satoh, Sumio Morioka
   Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. [Citation Graph (0, 0)][DBLP]
   ISC, 2002, pp:48-62 [Conf]
   
10. Akashi Satoh, Sumio Morioka
    Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. [Citation Graph (0, 0)][DBLP]
    ISC, 2003, pp:252-266 [Conf]
    
11. Akashi Satoh
    Hardware Architecture and Cost Estimates for Breaking SHA-1. [Citation Graph (0, 0)][DBLP]
    ISC, 2005, pp:259-273 [Conf]
    
12. Akashi Satoh, Tadanobu Inoue
    ASIC-Hardware-Focused Comparison for Hash Functions MD5, RIPEMD-160, and SHS. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:532-537 [Conf]
    
13. Shigenori Shimizu, Hiroshi Ishikawa, Akashi Satoh, Toru Aihara
    On-demand design service innovations. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2004, v:48, n:5-6, pp:751-766 [Journal]
    
14. Akashi Satoh, Tadanobu Inoue
    ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:1, pp:3-10 [Journal]
    
15. Akashi Satoh, Kohji Takano
    A Scalable Dual-Field Elliptic Curve Cryptographic Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:4, pp:449-460 [Journal]
    
16. Sumio Morioka, Akashi Satoh
    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:686-691 [Journal]
    
17. Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
    SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1847-1850 [Conf]
    
18. Akashi Satoh
    High-Speed Parallel Hardware Architecture for Galois Counter Mode. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1863-1866 [Conf]
    
19. Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh
    DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1807-1810 [Conf]
    
20. Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
    A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1859-1862 [Conf]
    
21. Akashi Satoh, Takeshi Sugawara, Takafumi Aoki
    High-Speed Pipelined Hardware Architecture for Galois Counter Mode. [Citation Graph (0, 0)][DBLP]
    ISC, 2007, pp:118-129 [Conf]
    
22. 
    High-Performance Concurrent Error Detection Scheme for AES Hardware. [Citation Graph (, )][DBLP]
    
    
23. 
    Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. [Citation Graph (, )][DBLP]
    
    
24. 
    A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. [Citation Graph (, )][DBLP]
    
    
25. 
    Chosen-message SPA attacks against FPGA-based RSA hardware implementations. [Citation Graph (, )][DBLP]
    
    
26. 
    Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. [Citation Graph (, )][DBLP]
    
    
27. 
    Systematic design of high-radix Montgomery multipliers for RSA processors. [Citation Graph (, )][DBLP]
    
    
28. 
    Enhanced power analysis attack using chosen message against RSA hardware implementations. [Citation Graph (, )][DBLP]
    
    
29. 
    High-performance ASIC implementations of the 128-bit block cipher CLEFIA. [Citation Graph (, )][DBLP]
    
    
30. 
    ASIC hardware implementations for 512-bit hash function Whirlpool. [Citation Graph (, )][DBLP]
    
    
31. 
    Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. [Citation Graph (, )][DBLP]
    
    
32. 
    Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. [Citation Graph (, )][DBLP]
    
    
33. 
    Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules. [Citation Graph (, )][DBLP]
    
    
34. 
    Is the differential frequency-based attack effective against random delay insertion? [Citation Graph (, )][DBLP]
    
    
35. 
    Enhanced Correlation Power Analysis Using Key Screening Technique. [Citation Graph (, )][DBLP]