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John Wawrzynek: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nicholas Weaver, John Wawrzynek
    A Comparison of the AES Candidates Amenability to FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    AES Candidate Conference, 2000, pp:28-39 [Conf]
  2. John Lazzaro, John Wawrzynek
    A multi-sender asynchronous extension to the AER protocol. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:158-171 [Conf]
  3. David E. Culler, Anurag Sah, Klaus E. Schauser, Thorsten von Eicken, John Wawrzynek
    Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1991, pp:164-175 [Conf]
  4. Timothy J. Callahan, John Wawrzynek
    Adapting software pipelining for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:57-64 [Conf]
  5. André DeHon, John Wawrzynek
    Reconfigurable Computing: What, Why, and Implications for Design Automation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:610-615 [Conf]
  6. Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya
    A Two-Dimensional Topological Compactor With Octagonal Geometry. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:727-731 [Conf]
  7. Chen Chang, John Wawrzynek, Pierre-Yves Droz, Robert W. Brodersen
    The Design And Application Of A High-End Reconfigurable Computing System. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:129-136 [Conf]
  8. Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek
    Object Oriented Circuit-Generators in Java. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:158-166 [Conf]
  9. André DeHon, Randy Huang, John Wawrzynek
    Hardware-Assisted Fast Routing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:205-0 [Conf]
  10. Timothy J. Callahan, John Wawrzynek
    Datapath-oriented FPGA mapping and placement for configurable computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:234-235 [Conf]
  11. John R. Hauser, John Wawrzynek
    Garp: a MIPS processor with a reconfigurable coprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:12-21 [Conf]
  12. Nicholas Weaver, John Wawrzynek
    The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:303-0 [Conf]
  13. Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek
    Fast Module Mapping and Placement for Datapaths in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:123-132 [Conf]
  14. Randy Huang, John Wawrzynek, André DeHon
    Stochastic, spatial routing for hypergraphs, trees, and meshes. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:78-87 [Conf]
  15. Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon
    Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:196-205 [Conf]
  16. William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon
    HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:125-134 [Conf]
  17. Nicholas Weaver, John R. Hauser, John Wawrzynek
    The SFRA: a corner-turn FPGA architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:3-12 [Conf]
  18. Nicholas Weaver, Yury Markovskiy, Yatish Patel, John Wawrzynek
    Post-placement C-slow retiming for the xilinx virtex FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:185-194 [Conf]
  19. Timothy J. Callahan, John Wawrzynek
    Instruction-Level Parallelism for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:248-257 [Conf]
  20. Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon
    Stream Computations Organized for Reconfigurable Execution (SCORE). [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:605-614 [Conf]
  21. Zohair Hyder, John Wawrzynek
    Defect Tolerance in Multiple-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:247-254 [Conf]
  22. John Lazzaro, John Wawrzynek
    Silicon Models for Auditory Scene Analysis. [Citation Graph (0, 0)][DBLP]
    NIPS, 1995, pp:699-705 [Conf]
  23. John Lazzaro, John Wawrzynek, Richard Lippmann
    A Micropower Analog VLSI HMM State Decoder for Wordspotting. [Citation Graph (0, 0)][DBLP]
    NIPS, 1996, pp:727-733 [Conf]
  24. John Lazzaro, John Wawrzynek, Misha Mahowald, Massimo Sivilotti, Dave Gillespie
    Silicon Auditory Processors as Computer Peripherals. [Citation Graph (0, 0)][DBLP]
    NIPS, 1992, pp:820-827 [Conf]
  25. John Wawrzynek, Krste Asanovic, Brian Kingsbury, James Beck, David Johnson, Nelson Morgan
    SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training. [Citation Graph (0, 0)][DBLP]
    NIPS, 1995, pp:619-625 [Conf]
  26. John Lazzaro, John Wawrzynek
    A case for network musical performance. [Citation Graph (0, 0)][DBLP]
    NOSSDAV, 2001, pp:157-166 [Conf]
  27. Timothy J. Callahan, John R. Hauser, John Wawrzynek
    The Garp Architecture and C Compiler. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:4, pp:62-69 [Journal]
  28. John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, Nelson Morgan
    Spert-II: A Vector Microprocessor System. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:3, pp:79-86 [Journal]
  29. Chen Chang, John Wawrzynek, Robert W. Brodersen
    BEE2: A High-End Reconfigurable Computing System. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:2, pp:114-125 [Journal]
  30. Krste Asanovic, James Beck, Jerry Feldman, Nelson Morgan, John Wawrzynek
    Designing A Connectionist Network Supercomputer. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1993, v:4, n:4, pp:317-326 [Journal]
  31. John Wawrzynek, Keith Diefendorff
    Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:2, pp:8-11 [Journal]
  32. John Lazzaro, John Wawrzynek
    JPEG Quality Transcoding Using Neural Networks Trained With a Perceptual Error Measure. [Citation Graph (0, 0)][DBLP]
    Neural Computation, 1999, v:11, n:1, pp:267-296 [Journal]
  33. André DeHon, Randy Huang, John Wawrzynek
    Stochastic spatial routing for reconfigurable networks. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:301-318 [Journal]
  34. André DeHon, Yury Markovskiy, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek
    Stream computations organized for reconfigurable execution. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:334-354 [Journal]
  35. John Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic
    RAMP: Research Accelerator for Multiple Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:2, pp:46-57 [Journal]

  36. High-throughput bayesian computing machine with reconfigurable hardware. [Citation Graph (, )][DBLP]


  37. RAMP Blue: A Message-Passing Manycore System in FPGAs. [Citation Graph (, )][DBLP]


  38. Adventures with a Reconfigurable Research Platform. [Citation Graph (, )][DBLP]


  39. ParaLearn: a massively parallel, scalable system for learning interaction networks on FPGAs. [Citation Graph (, )][DBLP]


  40. A design methodology for domain-optimized power-efficient supercomputing. [Citation Graph (, )][DBLP]


  41. Using adaptive routing to compensate for performance heterogeneity. [Citation Graph (, )][DBLP]


  42. A view of the parallel computing landscape. [Citation Graph (, )][DBLP]


  43. Workloads of the Future. [Citation Graph (, )][DBLP]


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