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Edward J. Nowak: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Kerry Bernstein, John E. Bertsch, William F. Clark, John J. Ellis-Monaghan, Larry G. Heller, Edward J. Nowak
Practical performance/power alternatives within an existing CMOS technology generation. [Citation Graph (0, 0)][DBLP]
ISLPED, 1996, pp:365-370 [Conf] - Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. [Citation Graph (0, 0)][DBLP]
VLSI Design, 2007, pp:665-672 [Conf] - Edward J. Nowak
Maintaining the benefits of CMOS scaling when scaling bogs down. [Citation Graph (0, 0)][DBLP]
IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:169-186 [Journal] - Ernest Y. Wu, Edward J. Nowak, Alex Vayshenker, Wing L. Lai, David L. Harmon
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics. [Citation Graph (0, 0)][DBLP]
IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:287-298 [Journal]
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