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Kyu-won Choi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kyu-won Choi, Abhijit Chatterjee
    HA2TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:207-212 [Conf]
  2. Kyu-won Choi, Abhijit Chatterjee
    UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:72-77 [Conf]
  3. Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy
    System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:225-230 [Conf]
  4. Kyu-won Choi, Abhijit Chatterjee
    Efficient instruction-level optimization methodology for low-power embedded systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:147-152 [Conf]
  5. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee
    An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:173-182 [Conf]
  6. Kyu-won Choi, Abhijit Chatterjee
    PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:178-187 [Conf]

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