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Koushik K. Das :
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Koushik K. Das , Rajiv V. Joshi , Ching-Te Chuang , Peter W. Cook , Richard B. Brown New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:168-171 [Conf ] Keunwoo Kim , Koushik K. Das , Rajiv V. Joshi , Ching-Te Chuang Nanoscale CMOS circuit leakage power reduction by double-gate device. [Citation Graph (0, 0)][DBLP ] ISLPED, 2004, pp:102-107 [Conf ] Koushik K. Das , Richard B. Brown Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2003, pp:29-34 [Conf ] Koushik K. Das , Richard B. Brown Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2003, pp:291-296 [Conf ] Koushik K. Das , Shih-Hsien Lo , Ching-Te Chuang High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2006, pp:758-761 [Conf ] Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.001secs