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Publications of Author

1. Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang
   Nanoscale CMOS circuit leakage power reduction by double-gate device. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2004, pp:102-107 [Conf]
   
2. Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang
   Strained-si devices and circuits for low-power applications. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:180-183 [Conf]
   
3. Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy
   Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2005, pp:8-13 [Conf]
   
4. Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim
   Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   ISQED, 2003, pp:153-158 [Conf]
   
5. Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
   Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. [Citation Graph (0, 0)][DBLP]
   ISQED, 2005, pp:410-415 [Conf]
   
6. Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong
   Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:145-152 [Conf]
   
7. Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang
   A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2007, pp:665-672 [Conf]
   
8. 
   Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]
   
   
9. 
   A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. [Citation Graph (, )][DBLP]
   
   
10. 
    Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. [Citation Graph (, )][DBLP]
    
    
11. 
    Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. [Citation Graph (, )][DBLP]
    
    
12. 
    Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. [Citation Graph (, )][DBLP]
    
    
13. 
    Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. [Citation Graph (, )][DBLP]
    
    
14. 
    FinFET SRAM Design. [Citation Graph (, )][DBLP]