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Takahiro Hanyu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi
    A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:170-175 [Conf]
  2. Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama
    Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:92-97 [Conf]
  3. Takahiro Hanyu
    Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:241-0 [Conf]
  4. Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama
    Quaternary Universal-Literal CAM for Cellular Logic Image Processing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:224-229 [Conf]
  5. Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama
    One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:175-0 [Conf]
  6. Takahiro Hanyu, Tatsuo Higuchi
    Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:18-23 [Conf]
  7. Takahiro Hanyu, Tatsuo Higuchi
    A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:24-31 [Conf]
  8. Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
    Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:382-0 [Conf]
  9. Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
    Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1999, pp:275-279 [Conf]
  10. Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi
    A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:16-23 [Conf]
  11. Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama
    DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:423-429 [Conf]
  12. Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama
    Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1999, pp:30-35 [Conf]
  13. Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, C. Zukeran
    Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:167-172 [Conf]
  14. Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
    Multiple-Valued Dynamic Source-Coupled Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:207-212 [Conf]
  15. Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
    Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:19-26 [Conf]
  16. Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
    Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:64-0 [Conf]
  17. Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama
    Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:134-139 [Conf]
  18. Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi
    Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:274-281 [Conf]
  19. Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama
    Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:99-104 [Conf]
  20. Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama
    Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:270-275 [Conf]
  21. Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
    Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:21-26 [Conf]
  22. Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
    Fully Source-Coupled Logic Based Multiple-Valued VLSI. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:270-275 [Conf]
  23. Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama
    Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:438-0 [Conf]
  24. Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama
    Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:161-0 [Conf]
  25. Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu
    A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:340-345 [Conf]
  26. Akira Mochizuki, Takahiro Hanyu
    Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:5- [Conf]
  27. Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu
    Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:14- [Conf]
  28. Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu
    Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:192-197 [Conf]
  29. Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu
    Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:138-143 [Conf]
  30. Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu
    A Multiple-Valued Ferroelectric Content-Addressable Memory. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:74-79 [Conf]
  31. Tomohiro Takahashi, Takahiro Hanyu
    Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:20-25 [Conf]
  32. Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
    Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. [Citation Graph (0, 0)][DBLP]
    PRDC, 2000, pp:27-36 [Conf]
  33. Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama
    Design and evaluation of a digit-parallel multiple-valued content-addressable memory. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1998, v:29, n:11, pp:48-54 [Journal]
  34. Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama
    Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1998, v:29, n:11, pp:40-47 [Journal]

  35. Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. [Citation Graph (, )][DBLP]


  36. MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. [Citation Graph (, )][DBLP]


  37. Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. [Citation Graph (, )][DBLP]


  38. Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme. [Citation Graph (, )][DBLP]


  39. Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. [Citation Graph (, )][DBLP]


  40. High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. [Citation Graph (, )][DBLP]


  41. High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. [Citation Graph (, )][DBLP]


  42. Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. [Citation Graph (, )][DBLP]


  43. Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control. [Citation Graph (, )][DBLP]


  44. Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. [Citation Graph (, )][DBLP]


  45. One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control. [Citation Graph (, )][DBLP]


  46. Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control. [Citation Graph (, )][DBLP]


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