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Katsuhiko Degawa:
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Publications of Author
 Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
A FieldProgrammable Digital Filter Chip Using MultipleValued CurrentMode Logic. [Citation Graph (0, 0)][DBLP] ISMVL, 2003, pp:213220 [Conf]
 Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
A HighDensity Ternary ContentAddressable Memory Using SingleElectron Transistors. [Citation Graph (0, 0)][DBLP] ISMVL, 2006, pp:19 [Conf]
 Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
A SingleElectronTransistor Logic Gate Family and Its Application  Part I: Basic Components for Binary, MultipleValued and MixedMode Logic. [Citation Graph (0, 0)][DBLP] ISMVL, 2004, pp:262268 [Conf]
 Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
A TwoBitperCell ContentAddressable Memory Using SingleElectron Transistors. [Citation Graph (0, 0)][DBLP] ISMVL, 2005, pp:3238 [Conf]
 Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
A SingleElectronTransistor Logic Gate Family and Its Application  Part II: Design and Simulation of a 73 Parallel Counter with Linear Summation and MultipleValued Latch Functions. [Citation Graph (0, 0)][DBLP] ISMVL, 2004, pp:269274 [Conf]
HighLevel Design of MultipleValued Arithmetic Circuits Based on Arithmetic Description Language. [Citation Graph (, )][DBLP]
AlgorithmLevel Optimization of MultipleValued Arithmetic Circuits Using Counter Tree Diagrams. [Citation Graph (, )][DBLP]
Phasebased alignment of two signals having partially overlapped spectra. [Citation Graph (, )][DBLP]
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