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Yasuo Takahashi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
    A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:19- [Conf]
  2. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
    A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:262-268 [Conf]
  3. Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
    A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:32-38 [Conf]
  4. Hiroshi Inokawa, Yasuo Takahashi
    Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:259-266 [Conf]
  5. Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
    A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:269-274 [Conf]
  6. Yasuo Takahashi, Akira Fujiwara, Yukinori Ono, Katsumi Murase
    Silicon Single-Electron Devices and Their Applications. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:411-0 [Conf]

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